Methods and apparatus for implementing a saturating multiplier

1. A method for performing multiplication on a programmable chip, the method comprising:

performing a multiply operation using a multiplier;

saturating the result of the multiplier by using saturating addition/subtraction (add/sub) logic; and,

accumulating by using the saturating add/sub logic;

wherein saturating the result of the multiplier occurs before accumulating by using the saturating add/sub logic.

2. The method of claim 1 , wherein a multiplier is provided with a first input A and a second input B.

3. The method of claim 2 , wherein the first input A and the second input B are 16 bit values.

4. The method of claim 2 , wherein the first input A and the second input B are 16-bit values provided in 1q15 format.

5. The method of claim 2 , wherein the multiplier provides a product M to an extractor.

6. The method of claim 5 , wherein the product is a 32-bit product wherein the inputs A and B are 16-bit values.

7. The method of claim 6 , wherein the extractor formats the 32-bit product into 1q15 format.

8. The method of claim 5 , wherein the product M is provided as a first operand to an adder.

9. The method of claim 8 , wherein a value Z is provided as the second operand to the adder.

10. The method of claim 9 , wherein the result of the adder is stored in a result register.

11. The method of claim 10 , wherein the result is then saturated and provided as the value Z.

12. A programmable chip, comprising:

a signed multiplier configured to receive a first input A and a second input B, the signed multiplier configured to provide an output C;

an extractor configured to take the output C and truncate the output to provide a truncated value M;

modified adder configured to take truncated value M as a first input, modify M, and provide a value D;

a saturation block operable to saturate the value D to provide a value Z as the second input to the adder.

13. The programmable chip of claim 12 , wherein a multiplier is provided with a first input A and a second input B.

14. The programmable chip of claim 13 , wherein the first input A and the second input B are 16 bit values.

15. The programmable chip of claim 13 , wherein the first input A and the second input B are 16-bit values provided in 1q15 format.

16. The programmable chip of claim 12 , wherein the extractor formats the 32-bit product into 1q15 format.

17. The programmable chip of claim 12 , wherein the value D is stored in a result register.

18. The programmable chip of claim 17 , wherein the adder is implemented using 18 logic elements.

19. The programmable chip of claim 17 , wherein the saturation block is implemented using 17 logic elements.

20. The programmable chip of claim 19 , wherein each logic element comprises a sum block and a carry block.

21. A device, comprising:

means for performing a multiply operation using a multiplier;

means for accumulating by using a saturating addition/subtraction (add/sub) logic;

means for storing a result of the means for accumulating;

means for saturating the result of the multiplier before accumulating by using the saturating add/sub logic.

22. The device of claim 21 , wherein a multiplier is provided with a first input A and a second input B.

23. The device of claim 22 , wherein the first input A and the second input B are 16 bit values.

24. The device of claim 22 , wherein the first input A and the second input B are 16-bit values provided in 1q15 format.

25. The device of claim 22 , wherein the multiplier provides a product M to an extractor.

26. The device of claim 25 , wherein the product is a 32-bit product wherein the inputs A and B are 16-bit values.