CRC circuits with extended cycles
View Patent ↗A structure for a parallel cyclic redundancy check (CRC) structure in which the number of cycles in the loopback can be arbitrarily extended is provided. The parallel CRC structure includes a reweighting module in the feedback loop that is pipelined into multiple stages. The parallel CRC structure also includes multiple feed forward reweighting modules that correspond to the multiple pipeline stages in the feedback loop. The reweighting module in the feedback loop accumulates and reweights the contribution of all symbols in the message, while the N reweighting modules in the N parallel feed-forward paths provide the contributions of the symbols that are “in-flight” within the feedback loop to the final CRC checksum.
1. An integrated circuit (IC) comprising:
a cyclic redundancy check (CRC) circuit that receives a message and that includes:
a loopback path comprising a plurality of pipeline stages;
an exclusive-OR adder circuit; and
a plurality of feed-forward paths, wherein each feed-forward path is coupled between the exclusive-OR adder circuit and a respective pipeline stage of the plurality of pipeline stages in the loopback path,
receives input signals from the respective pipeline stage, and provides output signals to the exclusive-OR adder circuit.
2. The IC of claim 1 , wherein the message comprises a plurality of symbols, the CRC circuit further comprising:
a reduce module coupled to an input of the loopback path, wherein the reduce module receives one symbol of the plurality of symbols per clock cycle, wherein the reduce module converts each symbol of the plurality of symbols into a symbol CRC checksum corresponding to that symbol to generate a plurality of symbol CRC checksums, and wherein the reduce module provides the symbol CRC checksums to the pipeline stages of the loopback path through the input of the loopback path.
3. The IC of claim 2 , wherein the CRC circuit comprises a plurality of reweighting modules in the plurality of feed-forward paths that generate a plurality of weighted symbol CRC checksums, wherein each reweighting module of the plurality of reweighting modules receives a respective symbol CRC checksum of the plurality of symbol CRC checksums from a respective pipeline stage of the plurality of pipeline stages, and reweighs the respective symbol CRC checksum to generate a weighted symbol CRC checksum of the plurality of weighted symbol CRC checksums.
4. The IC of claim 3 , wherein the loopback path comprises at least one loopback reweighting module.
5. The IC of claim 3 , wherein the plurality of reweighting modules comprises a plurality of feed-forward reweighting modules, wherein each feed-forward reweighting module of the plurality of feed-forward reweighting modules is in a respective feed-forward path of the plurality of feed-forward paths.
6. The IC of claim 3 , wherein each reweighting module of the plurality of reweighting modules performs a different number of bit-shifts from each other reweighting module of the plurality of reweighting modules when reweighing the respective symbol CRC checksum.
7. The IC of claim 3 , wherein the loopback path accumulates the symbol CRC checksums for the plurality of symbols.
8. The IC of claim 7 , wherein the plurality of feed-forward paths provide the weighted symbol CRC checksums to the exclusive-OR adder circuit.
9. A method for configuring an integrated circuit (IC) comprising a plurality of configurable circuits, the method comprising:
forming a loopback path comprising a plurality of pipeline stages;
forming an exclusive-OR adder circuit; and
forming a plurality of feed-forward paths, wherein each feed-forward path of the plurality of feed-forward paths is coupled between the exclusive-OR adder circuit and a respective pipeline stage of the plurality of pipeline stages in the loopback path, receives input signals from the respective pipeline stage, and provides output signals to the exclusive-OR adder circuit.
10. The method of claim 9 , further comprising:
forming a reduce module coupled to an input of the loopback path, wherein the reduce module receives a message that comprises a plurality of symbols, wherein the reduce module converts each symbol of the plurality of symbols into a symbol CRC checksum for that symbol to generate a plurality of symbol CRC checksums, and wherein the reduce module provides the symbol CRC checksums to the pipeline stages of the loopback path through the input of the loopback path.
11. The method of claim 10 , wherein each feed-forward path of the plurality of feed-forward paths comprises a reweighting module for reweighing a respective symbol CRC checksum of the plurality of symbol CRC checksums to generate a plurality of weighted symbol CRC checksums.
12. The method of claim 11 , wherein each reweighting module reweighs the respective symbol CRC checksum of the plurality of symbol CRC checksums by performing a respectively different number of bit-shifts on the respective symbol CRC checksum compared to bit-shifts performed by each other reweighting module on each other symbol CRC checksum.
13. The method of claim 10 , wherein the loopback path accumulates the symbol CRC checksums for the plurality of symbols.
14. The method of claim 13 , wherein the plurality of feed-forward paths provide the weighted symbol CRC checksums to the exclusive-OR adder circuit.