Systems and methods for detecting and mitigating of programmable logic device tampering
View Patent ↗Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation.
1. A logic device configured to prevent tampering, comprising:
programmable logic circuitry of a core of the logic device comprising a plurality of logic array blocks, a plurality of logical connections, and configuration memory, wherein the programmable logic circuitry is configured to implement a user design of the plurality of the logic array blocks and the plurality of logical connections based on values stored in the configuration memory to program a first function of the programmable logic circuitry;
control circuitry coupled to the programmable logic circuitry, wherein the control circuitry is configured to:
determine that a configuration attempt of the programmable logic circuitry is valid based at least in part on an authentication bit asserting a first logical state, wherein the configuration attempt is associated with an unauthorized bitstream configured to program a second function of the programmable logic circuitry;
cause a counter to be decremented in response to determining that the configuration attempt is not valid, wherein the configuration attempt is determined to be invalid in response to the authentication bit asserting a second logical state opposite the first logical state;
clear the configuration memory in response to the counter reaching a threshold value, wherein clearing the configuration memory resets at least some of the plurality of logic array blocks and the plurality of logical connections of the programmable logic circuitry implementing the user design; and
clear an encryption key associated with decrypting configuration data associated with the programmable logic circuitry in response to the counter reaching the threshold value; and
a memory device coupled to the control circuitry, wherein the memory device comprises a battery configured to back up at least a portion of the memory device.
2. The logic device of claim 1 , wherein the control circuitry is configured to modify the counter based on a successful configuration of the programmable logic circuitry.
3. The logic device of claim 2 , wherein the control circuitry is configured to modify the counter by incrementing the counter based on the successful configuration.
4. The logic device of claim 1 , wherein the encryption key is stored in the memory device and is backed up by the battery.
5. The logic device of claim 1 , wherein the counter is stored in the memory device and is backed up by the battery.
6. The logic device of claim 1 , wherein an initial value of the counter is configured to be set by a user.
7. The logic device of claim 1 , wherein the threshold value is zero.
8. The logic device of claim 1 , comprising a field programmable gate array.
9. A system configured to prevent tampering, comprising:
a logic device comprising:
core configuration fabric comprising a plurality of logic array blocks, a plurality of logical connections, and configuration memory, wherein the core configuration fabric is configured to implement a user design of the plurality of the logic array blocks and the plurality of logical connections based on values stored in the configuration memory to program a first function of the core configuration fabric; and
control circuitry coupled to the core configuration fabric, wherein the control circuitry is configured to:
determine that a configuration attempt of the core configuration fabric is invalid based at least in part on an authentication bit asserting a first logical state, wherein the configuration attempt is associated with an unauthorized bitstream configured to program a second function of the core configuration fabric;
cause a counter to be decremented in response to determining the configuration attempt was invalid, wherein the configuration attempt is determined to be invalid in response to the authentication bit asserting a second logical state opposite of the first logical state;
clear the configuration memory in response to the counter reaching a threshold value, wherein clearing the configuration memory initializes the plurality of logic array blocks and the plurality of logical connections and removes the user design; and
clear an encryption key associated with decrypting configuration data associated with programmable logic circuitry in response to thecounter reaching the threshold value;
a memory device coupled to the control circuitry, wherein the memory device comprises a battery configured to back up at least a portion of the memory device; and
a processor coupled to the logic device.
10. The system of claim 9 , wherein the control circuitry is configured to receive the configuration attempt from a source external to the system.
11. The system of claim 9 , wherein the system comprises a computer networking system.
12. The system of claim 9 , wherein the system comprises a data networking system.
13. The system of claim 9 , wherein the system comprises an instrumentation system.
14. The system of claim 9 , wherein the system comprises a video processing system.
15. The system of claim 9 , wherein the system comprises a digital signal processing system.