IP Library Granted Patent US 9,998,275
Granted Patent B1
US 9,998,275 · App. 14/694,785 · Granted Jun 12, 2018

Digital monobit dithering circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,998,275
App. No.
14/694,785
Granted
Jun 12, 2018
Kind
B1
Abstract

Techniques and mechanisms disclosed herein add dithering noise to a receiver to reduce harmonics.

Claims (24)

1. A circuit comprising:

a receiver having a first input, a second input, and an output, the receiver to provide sampled data of a data signal associated with the first input at its output based on a comparison of a first voltage at the first input and a second voltage at the second input, the first voltage corresponding to the data signal offset by a first reference voltage at the first input; and

a noise source having an output coupled with the second input of the receiver, the noise source to provide a noise signal at its output, the second voltage at the second input of the receiver corresponding to the noise signal offset by to a second reference voltage.

2. The circuit of claim 1 , wherein the noise source includes a transmitter.

3. The circuit of claim 2 , wherein the receiver and the transmitter are components of a transceiver.

4. The circuit of claim 2 , wherein the receiver and the transmitter are components of different transceivers.

5. The circuit of claim 1 , wherein the data signal is alternating current (AC) coupled with the first reference voltage at the first input, and the noise signal is AC coupled with the second reference voltage at the second input.

6. The circuit of claim 1 , wherein the noise source comprises:

a bit generator to generate bits; and

a transmitter coupled with the bit generator and to generate the noise signal based on the generated bits.

7. The circuit of claim 1 , wherein the first input and the second input are differential inputs of the receiver.

8. The circuit of claim 1 , wherein the noise source includes a transmitter, and the circuit further comprises:

an analysis circuit to analyze the sampled data and adjust a voltage swing of the transmitter based on the analysis of the sampled data to increase a magnitude of the noise signal.

9. The circuit of claim 1 , wherein the first reference voltage and the second reference voltage are the same voltage.

10. A method for dithering, the method comprising:

providing a first reference voltage to a first input and a second reference voltage to a second input of a receiver;

applying a data signal to the first reference voltage to provide a first combined voltage at the first input of the receiver;

applying a noise signal to the second reference voltage to provide a second combined voltage at the second input of the receiver; and

generating, by the receiver, an output signal based on a comparison of the first combined voltage and the second combined voltage.

11. The method of claim 10 , further comprising:

generating, by a transmitter, the noise signal to be applied to the second reference voltage at the second input of the receiver.

12. The method of claim 11 , further comprising:

adjusting a voltage swing of the transmitter based on an analysis of the output signal, the adjustment of the voltage swing adjusting a magnitude of the noise signal.

13. The method of claim 10 , wherein the data signal and the noise signal are applied by AC coupling the data signal to the first input of the receiver and AC coupling the noise signal to the second input of the receiver.

Assignments (2)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2015
From: PRITSKER, DAN
To: ALTERA CORPORATION
Reel/Frame 035487/0800 →