Parallel low and asymmetric rate Reed Solomon coding

1. Codeword processing circuitry comprising:

decoding circuitry comprising:

syndrome computation circuitry configured to:

receive a codeword encoded with a first number of check symbols; and

asymmetrically process the received codeword according to a second number of check symbols, wherein the second number of check symbols is less than the first number of check symbols, to produce a plurality of syndrome values;

error locator polynomial circuitry configured to:

process the plurality of syndrome values to produce an error locator polynomial and an error evaluator polynomial corresponding to the received codeword,

produce a derivative of the error locator polynomial by outputting a first polynomial term and a second polynomial term, wherein the second polynomial term is a constant,

output an inverse of a denominator of the first polynomial term using a variable finite-field multiplier by processing a corresponding input over a plurality of clock cycles; and

data recovery circuitry configured to process the received codeword using a plurality of error values to produce a recovered codeword.

2. The codeword processing circuitry of claim 1 , wherein the decoding circuitry includes at most one variable finite-field divider, said at most one variable finite-field divider included in the error locator polynomial circuitry.

3. The codeword processing circuitry of claim 1 , wherein the decoding circuitry further comprises error search and calculation circuitry configured to produce the plurality of error values based on the error locator polynomial and the error evaluator polynomial, and wherein the decoding circuitry is further configured to provide the plurality of error values to the data recovery circuitry.

4. The codeword processing circuitry of claim 3 , wherein:

the decoding circuitry is further configured to provide the received codeword to a data delay buffer; and

the data delay buffer is configured to delay an output of the received codeword for a number of clock cycles required for the syndrome computation circuitry, the error locator polynomial circuitry, and the error search and calculation circuitry to asymmetrically process the received codeword.

5. The codeword processing circuitry of claim 3 , wherein the error search and calculation circuitry is further configured to:

perform an error search and calculation corresponding to each of p symbol locations of the received codeword in p parallel stages, wherein p is an integer greater than one; and

output a corresponding plurality of p error values in a clock cycle.

6. The codeword processing circuitry of claim 1 , wherein the error locator polynomial circuitry is further configured to output the inverse of the denominator of the first polynomial term by using an inverse power of a root of the error locator polynomial.

7. Decoding circuitry comprising:

syndrome computation circuitry configured to process a received codeword to produce a plurality of syndrome values;

error locator polynomial circuitry configured to:

process the plurality of syndrome values to produce an error locator polynomial and an error evaluator polynomial corresponding to the received codeword,

produce a derivative of the error locator polynomial by outputting a first polynomial term and a second polynomial term, wherein the second polynomial term is a constant, and

output an inverse of a denominator of the first polynomial term using a variable finite-field multiplier by processing a corresponding input over a plurality of clock cycles;

error search and calculation circuitry configured in a plurality of p parallel stages to output, in a single clock cycle, a corresponding plurality of p error values for the received codeword based on the error locator polynomial and the error evaluator polynomial, wherein p is an integer greater than one; and

codeword recovery circuitry configured to produce a recovered codeword by modifying the received codeword using the plurality of p error values.

8. The decoding circuitry of claim 7 , wherein the decoding circuitry includes exactly one variable divider, said variable divider included in the error locator polynomial circuitry.

9. The decoding circuitry of claim 7 , wherein the decoding circuitry includes p variable finite-field multipliers, wherein each variable finite-field multiplier of said p variable finite-field multipliers is included in a respective parallel stage of error search and calculation circuitry of the plurality of p parallel stages of the error search and calculation circuitry.

10. The decoding circuitry of claim 7 , wherein the decoding circuitry includes at most p variable finite-field multipliers and includes no variable dividers.

11. The decoding circuitry of claim 7 , wherein the error locator polynomial circuitry is further configured to output the inverse of the denominator of the first polynomial term by using an inverse power of a root of the error locator polynomial.

12. A method of processing a codeword comprising:

receiving a codeword encoded with a first number of check symbols;

asymmetrically processing the received codeword according to a second number of check symbols, wherein the second number of check symbols is less than the first number of check symbols, to produce a plurality of syndrome values;

processing the plurality of syndrome values to produce an error locator polynomial and an error evaluator polynomial corresponding to the received codeword and the second number of check symbols;

producing a derivative of the error locator polynomial by outputting a first polynomial term and a second polynomial term, wherein the second polynomial term is a constant;

outputting an inverse of a denominator of the first polynomial term using a variable finite-field multiplier by processing a corresponding input over a plurality of clock cycles;

producing a plurality of error values based on the error locator polynomial and the error evaluator polynomial; and

modifying the received codeword based on the plurality of error values to produce a recovered codeword.

13. The method of claim 12 , wherein producing the derivative of the error locator polynomial is performed using the variable finite-field multiplier and without use of a divider.

14. Decoding circuitry comprising:

error locator polynomial circuitry configured to:

process a received codeword according to a symmetric decoding scheme to produce an error locator polynomial and an error evaluator polynomial corresponding to the received codeword,

produce a derivative of the error locator polynomial by outputting a first polynomial term and a second polynomial term, wherein the second polynomial term is a constant, and

output an inverse of a denominator of the first polynomial term using a variable finite-field multiplier by processing a corresponding input over a plurality of clock cycles;

error search and calculation circuitry configured in a plurality of p parallel stages to output, in a single clock cycle, a corresponding plurality of p error values for the received codeword based on the error locator polynomial and the error evaluator polynomial and the symmetric decoding scheme, wherein p is an integer greater than one; and

codeword recovery circuitry configured to produce a recovered codeword by modifying the received codeword.

15. The decoding circuitry of claim 14 , wherein:

the received codeword is a (251, 255) encoded Reed-Solomon codeword, and

each of the error locator polynomial circuitry and the error search and calculation circuitry process the received codeword according to a symmetric (251, 255) Reed-Solomon decoding scheme.