Routing and programming for resistive switch arrays
Various structures and methods are disclosed related to routing and programming circuitry on integrated circuits (“IC”) that have arrays of programmable resistive switches. In some embodiments, routing structures utilize densely populated resistive switch arrays to provide for efficient selection circuits that route into and out of logic regions. In other embodiments, programming circuitry is provided to help maintain relatively consistent programming current throughout an array of resistive switches to be programmed. In other embodiments, methods are provided for programming resistive switches without violating given power constraints. These and other embodiments are described further herein.
1. Routing circuitry in an integrated circuit comprising:
a vertical channel having a first plurality of routing lines;
a horizontal channel having a second plurality of routing lines;
a first logic region having a first plurality of logic elements;
a second logic region adjacent to the first logic region having a second plurality of logic elements;
a single level selection circuit switch array coupled to the vertical channel, to the horizontal channel, to inputs of the first plurality of logic elements, and to outputs of the second plurality of logic elements through routing lines other than the routing lines of the first and second pluralities of routing lines; and
an additional single level selection circuit switch array, wherein the single level selection circuit switch array is further coupled to a first portion of the first plurality of routing lines and to a first portion of the second plurality of routing lines, and wherein the additional single level selection circuit switch array is coupled to a second portion of the first plurality of routing lines and to a second portion of the second plurality of routing lines.
2. The routing circuitry of claim 1 , wherein the single level selection circuit switch array is further coupled to outputs of the first plurality of logic elements.
3. The routing circuitry of claim 1 , wherein the single level selection circuit switch array comprises a resistive switch array.
4. The routing circuitry of claim 3 , wherein the resistive switch array selectively connects any input of the resistive switch array to any output of the resistive switch array.
5. The routing circuitry of claim 1 , wherein the additional single level selection circuit switch array is further coupled the first and second pluralities of logic elements.
6. The routing circuitry of claim 5 , wherein some routing lines of first portion of the first plurality of routing lines are included in the second portion of the first plurality of routing lines, and wherein some routing lines of the first portion of the second plurality of routing lines are included in the second portion of the second plurality of routing lines.
7. Routing circuitry in an integrated circuit comprising:
a vertical channel having a first plurality of routing lines;
a horizontal channel having a second plurality of routing lines;
a first logic region having a first plurality of logic elements;
a second logic region adjacent to the first logic region having a second plurality of logic elements;
a resistive switch array coupled to the vertical channel, to the horizontal channel, and to inputs of the first plurality of logic elements, wherein resistive switch elements of the resistive switch array occupy less die space per element of the integrated circuit than would be occupied by configuration random access memory and pass transistor switch programmable elements on the integrated circuit; and
an additional resistive switch array, wherein a portion of the first plurality of routing lines is coupled to both the resistive switch array and the additional resistive switch array, and wherein the first plurality of logic elements directly receives signals from the resistive switch array and the additional resistive switch array.
8. The routing circuitry of claim 7 , wherein the resistive switch array is further coupled to outputs of the first plurality of logic elements.
9. The routing circuitry of claim 7 , wherein the resistive switch array is further coupled to another portion of the first plurality of routing lines and to a first portion of the second plurality of routing lines, and wherein the additional resistive switch array is coupled to yet another portion of the first plurality of routing lines and to a second portion of the second plurality of routing lines.
10. The routing circuitry of claim 9 , wherein the additional resistive switch array is further coupled the first and second pluralities of logic elements.
11. The routing circuitry of claim 7 , wherein a portion of the second plurality of routing lines is coupled to both the resistive switch array and the additional resistive switch array.