Partitioning designs to facilitate certification
View Patent ↗This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical portion of the design while the first portion corresponds to a non-safety-critical portion. The method additionally includes generating first configuration settings for the first portion and generating second configuration settings for the second portion. The method additionally includes verifying, or providing to a third-party certification body for verification, the first configuration settings for the first portion and the second configuration settings for the second portion. The method further includes providing the configuration settings for the second portion for programming into a PLD.
1. A method comprising:
generating, by one or more computer systems, a hardware description language (HDL) implementation of a circuit design to be implemented on a programmable logic device (PLD);
partitioning, by the one or more computer systems, the circuit design into a first portion and a second portion, the first portion including an interface for coupling the first portion and the second portion;
generating, by the one or more computer systems, a netlist representation of the second portion;
generating, by the one or more computer systems, programming bits for the second portion based on the netlist representation of the second portion;
verifying by the one or more computer systems, or providing to a third-party certification body for verification, the programming bits for the second portion;
revising, by the one or more computer systems, the first portion after generating the netlist representation of the second portion;
generating, by the one or more computer systems, a netlist representation of the revised first portion; and
merging, by the one or more computer systems, the netlist representation corresponding to the previously-verified second portion with the netlist representation of the revised first portion.
2. The method of claim 1 , further comprising providing the merged netlist representation for programming into a PLD.
3. The method of claim 1 , wherein the second portion is a safety-critical portion that includes functions that require certification by an independent certification body as meeting functional safety requirements.
4. The method of claim 1 , further comprising analyzing the HDL implementation to generate a hierarchical implementation of the circuit design, wherein partitioning the circuit design into the first portion and the second portion is performed at the hierarchical representation level.
5. The method of claim 1 , wherein the programming bits for the second portion are generated in the form of a programming file that includes programming bits for the first portion and for the second portion.
6. The method of claim 5 , wherein the programming bits for the first portion are assigned default values.
7. The method of claim 1 , further comprising generating programming bits for the first portion based on the merged netlist representation.
8. The method of claim 7 , wherein the programming bits for the first portion are generated in the form of a programming file that includes the programming bits for the first portion and the programming bits for the second portion based on the merged netlist representation.
9. The method of claim 8 , further comprising generating an exclusion list of resources reserved for use by the second portion.
10. The method of claim 9 , further comprising using the exclusion list to ensure that the programming bits for the first portion do not use resources reserved for the second portion.
11. The method of claim 8 , further comprising generating a bit mask that includes a first set of bits each having a first logical value and a second set of bits each having a second logical value, each of the second set of bits being in a location of the bitmask that corresponds to a programming bit in the programming file that is used by the second portion.
12. The method of claim 11 , further comprising using the bitmask to verify that the programming bits in the programming file for the second portion have not been altered from the previously verified programming bits for the second portion.
13. A programmable logic device (PLD) formed by the process comprising:
generating, by one or more computer systems, a hardware description language (HDL) implementation of a circuit design to be implemented on a programmable logic device (PLD);
partitioning, by the one or more computer systems, the circuit design into a first portion and a second portion, the first portion including an interface for coupling the first portion and the second portion;
generating, by the one or more computer systems, a netlist representation of the second portion;
generating, by the one or more computer systems, programming bits for the second portion based on the netlist representation of the second portion;
verifying by the one or more computer systems, or providing to a third-party certification body for verification, the programming bits for the second portion;
revising, by the one or more computer systems, the first portion after generating the netlist representation of the second portion;
generating, by the one or more computer systems, a netlist representation of the revised first portion; and
merging, by the one or more computer systems, the netlist representation corresponding to the previously-verified second portion with the netlist representation of the revised first portion.
14. The PLD of claim 13 , wherein the second portion is a safety-critical portion that includes functions that require certification by an independent certification body as meeting functional safety requirements.
15. The PLD of claim 13 , wherein the process further comprises analyzing the HDL implementation to generate a hierarchical implementation of the circuit design, wherein partitioning the circuit design into the first portion and the second portion is performed at the hierarchical representation level.
16. The PLD of claim 13 , wherein the programming bits for the second portion are generated in the form of a programming file that includes programming bits for the first portion and for the second portion.
17. The PLD of claim 13 , wherein the process further comprises generating programming bits for the first portion based on the merged netlist representation.
18. The PLD of claim 17 , wherein the programming bits for the first portion are generated in the form of a programming file that includes the programming bits for the first portion and the programming bits for the second portion based on the merged netlist representation.
19. The PLD of claim 18 , wherein the process further comprises:
generating an exclusion list of resources reserved for use by the second portion; and
using the exclusion list to ensure that the programming bits for the first portion do not use resources reserved for the second portion.
20. The PLD of claim 18 , further comprising:
generating a bit mask that includes a first set of bits each having a first logical value and a second set of bits each having a second logical value, each of the second set of bits being in a location of the bitmask that corresponds to a programming bit in the programming file that is used by the second portion; and
using the bitmask to verify that the programming bits in the programming file for the second portion have not been altered from the previously verified programming bits for the second portion.