Method and apparatus for placing and routing partial reconfiguration modules
View Patent ↗A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.
1. A method for designing a system on a target device, comprising:
routing static logic modules and partial reconfigurable (PR) modules on the target device;
arbitrating routing resources that are in conflict from the routing to static logic modules and PR modules competing for the routing resources;
assigning unused routing resources from the routing to static logic modules and PR modules having conflicts; and
re-routing the static logic modules and PR modules having conflicts with the routing resources arbitrated and assigned.
2. The method of claim 1 , wherein routing PR modules on a target device comprises routing instances of a PR module serially.
3. The method of claim 1 , wherein routing PR modules on the target device comprises routing a first instance of a PR module in parallel with a second instance of the PR module.
4. The method of claim 1 , wherein routing the PR modules on the target device comprises preferentially selecting routing resources for a first instance of a PR module that are used by a second instance of the PR module over selecting other routing resources.
5. The method of claim 1 , wherein routing the static logic modules and the PR modules comprises selecting routing resources for the static logic modules and the PR modules that are unused by other static logic modules and PR modules preferentially over selecting routing resources that are used by the other static modules or PR modules.
6. The method of claim 1 , wherein arbitrating routing resources that are in conflict comprises assigning a routing resource in conflict to a module in response to one of a timing constraint or routing constraint.
7. The method of claim 1 , wherein each instance of the PR module comprises a different circuit description of the PR module and each of the different circuit descriptions interfaces with a same static logic components.
8. The method of claim 1 further comprising placing static logic modules prior to placing PR modules on the target device.
9. The method of claim 8 , wherein the PR modules are placed in parallel.
10. A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method comprising:
routing static logic modules and partial reconfigurable (PR) modules on a target device;
arbitrating routing resources that are in conflict from the routing to static logic modules and PR modules competing for the routing resources;
assigning unused routing resources from the routing to static logic modules and PR modules having conflicts; and
re-routing the static logic modules and PR modules having conflicts with the routing resources arbitrated and assigned.
11. The non-transitory computer readable medium of claim 10 , wherein routing PR modules on a target device comprises routing instances of a PR module serially.
12. The non-transitory computer readable medium of claim 10 , wherein routing PR modules on the target device comprises routing a first instance of a PR module in parallel with a second instance of the PR module.
13. The non-transitory computer readable medium of claim 10 , wherein routing the PR modules on the target device comprises preferentially selecting routing resources for a first instance of a PR module that are used by a second instance of the PR module over selecting other routing resources.
14. The non-transitory computer readable medium of claim 10 , wherein routing the static logic modules and the PR modules comprises selecting routing resources for the static logic modules and the PR modules that are unused by other static logic modules and PR modules preferentially over selecting routing resources that are used by the other static modules or PR modules.
15. The non-transitory computer readable medium of claim 10 , wherein arbitrating routing resources that are in conflict comprises assigning a routing resource in conflict to a module in response to one of a timing constraint or routing constraint.
16. The non-transitory computer readable medium of claim 10 , wherein each instance of the PR module comprises a different circuit description of the PR module and each of the different circuit descriptions interfaces with a same static logic components.
17. The non-transitory computer readable medium of claim 10 , wherein the method further comprises placing static logic modules prior to placing PR modules on the target device.
18. The non-transitory computer readable medium of claim 17 , wherein the PR modules are placed in parallel.
19. A system designer, comprising:
a routing unit that routes static logic modules and partial reconfigurable (PR) modules on the target device;
an arbitration unit that routes resources that are in conflict from the routing to static logic modules and PR modules competing for the routing resources;
an assignment unit that assigns unused routing resources from the routing to static logic modules and PR modules having conflicts, wherein the routing unit re-routes the static logic modules and PR modules having conflicts with the routing resources arbitrated and assigned, wherein at least one of the routing unit, arbitration unit, and assignment unit is implemented by a processor.