Overcoming retiming limitations due to initial conditions conflicts

1. A computer-implemented method, comprising:

performing retiming using a first circuit design to determine one or more variations to the first circuit design;

identifying one or more source registers that are involved in one or more unsuccessful retiming moves due to initial conditions conflicts, wherein the initial conditions conflicts occur when a retimer unsuccessfully determines power-up states for intermediate registers in the one or more variations to the first circuit design to exhibit functionally equivalent behavior as the first circuit design;

displaying, via a graphical user interface, one or more selectively enablable recommendations indicating at least a portion of the one or more source registers for which one or more corrective actions can be performed;

receiving user input indicative of a selection of at least one of the one or more recommendations; and

generating a second circuit design in which a portion of the one or more corrective actions are performed to the portion of the one or more source registers corresponding to the at least one of the one or more recommendations indicated by the user input.

2. The method of claim 1 , comprising calculating a performance improvement for the one or more variations if the one or more corrective actions are implemented.

3. The method of claim 1 , wherein the one or more corrective actions to the one or more source registers will avoid the initial conditions conflicts.

4. The method of claim 1 , comprising causing the second circuit design to be programmed onto an integrated circuit.

5. The method of claim 4 , comprising causing the second circuit design to be programmed onto the integrated circuit by:

generating a bitstream representative of the second circuit design; and

providing the bitstream to the integrated circuit to program the integrated circuit.

6. The method of claim 1 , wherein the one or more source registers are included in the first circuit design.

7. The method of claim 1 , wherein functionally equivalent behavior comprises producing an equivalent output state as the first circuit design.

8. The method of claim 1 , wherein the one or more corrective actions comprise changing a value of the one or more source registers to a “don't care” value, configuring the one or more source registers to be power-up state agnostic, or both, wherein the “don't care” value can be set to either a logical 1 or a logical 0.

9. A tangible, non-transitory, computer-readable medium, comprising instructions that, when executed by a processor, are configured to cause the processor to:

perform retiming using a first circuit design to determine one or more variations to the first circuit design;

identify one or more source registers that are involved in one or more unsuccessful retiming moves due to initial conditions conflicts, wherein the initial conditions conflicts occur when a retimer unsuccessfully determines power-up states for intermediate registers in the one or more variations to the first circuit design to exhibit functionally equivalent behavior as the first circuit design;

cause a graphical user interface on an electronic display to display one or more selectively enablable recommendations indicating at least a portion of the one or more source registers for which one or more corrective actions can be performed;

receive user input indicative of a selection of at least one of the one or more recommendations; and

generate a second circuit design in which a portion of the one or more corrective actions are performed to the portion of the one or more source registers corresponding to the at least one of the one or more recommendations indicated by the user input.

10. The tangible, non-transitory, computer-readable medium of claim 9 , wherein the one or more unsuccessful retiming moves comprise moving the one or more source registers backwards past one or more combinational elements.

11. The tangible, non-transitory, computer-readable medium of claim 9 , wherein the instructions, when executed, are configured to cause the processor to cause the second circuit design to be programmed onto an integrated circuit.

12. The tangible, non-transitory, computer-readable medium of claim 9 , wherein the one or more corrective actions comprise changing a value of the one or more source registers to a “don't care” value, configuring the one or more source registers to be power-up state agnostic, or both, wherein the “don't care” value can be set to either a logical 1 or a logical 0.

13. The tangible, non-transitory, computer-readable medium of claim 9 , wherein the one or more source registers are included in the first circuit design represented by a register-transfer level (RTL) description.

14. The tangible, non-transitory, computer-readable medium of claim 9 , wherein the instructions, when executed, are configured to cause the processor to calculate a performance improvement for the one or more variations if the one or more corrective actions are implemented.

15. The tangible, non-transitory, computer-readable medium of claim 14 , wherein the instructions, when executed, are configured to cause the processor to cause the graphical user interface to display the performance improvement for the one or more variations.

16. The tangible, non-transitory, computer-readable medium of claim 9 , wherein the instructions, when executed, are configured to cause the processor to cause the graphical user interface to display the identified one or more source registers involved in the one or more unsuccessful retiming moves.

17. A circuit design component executed in a processor, comprising:

a retimer that:

receives a first circuit design;

determines a plurality of variations of the first circuit design;

identifies one or more source registers involved in one or more unsuccessful retiming moves due to initial conditions conflicts, wherein the initial conditions conflicts occur when the retimer unsuccessfully determines power-up states for intermediate registers in the one or more variations to the first circuit design to exhibit functionally equivalent behavior as the first circuit design; and

determines one or more selectively enablable recommendations indicating at least a portion of the one or more source registers for which one or more corrective actions can be performed; and

a graphical user interface (GUI) that:

displays an identity of the one or more source registers involved in the one or more unsuccessful retiming moves and one or more recommendations each comprising at least one of the one or more corrective actions, wherein the one or more recommendations are selectively enablable such that, for each of the one or more recommendations that is selected to be implemented, an associated corrective action of the corrective actions will be implemented to a corresponding source register of the one or more source registers; and

receives user input indicative of the selected recommendations of the one or more recommendations;

wherein the retimer is configured to generate a second circuit design in which a portion of the one or more corrective actions are performed to the portion of the one or more source registers based on the user input.

18. The circuit design component of claim 17 , configured, via the processor, to cause the second circuit design to be implemented on an integrated circuit.

19. The circuit design component of claim 17 , wherein the one or more corrective actions comprise changing a value of the one or more source registers to a value that can be set to either a logical 1 or a logical 0.

20. The circuit design component of claim 17 , wherein the retimer calculates a performance improvement for the one or more variations that would likely occur when the one or more corrective actions are implemented.