Methods and apparatus for embedding an error correction code in storage circuits
A computer-aided design (CAD) tool may identify don't care bits in configuration data. The don't care bits in the configuration data may change polarity without affecting the functionality of the circuit design. The CAD tool may compute an error check code (e.g., parity bits for a two-dimensional parity check) and insert the error check code into the configuration data. As an example, the CAD tool may replace don't care bits in the configuration data with the error code. The configuration data may be stored in configuration memory cells on a programmable integrated circuit, thereby implementing the circuit design with the error code on the programmable integrated circuit. During execution, the programmable integrated circuit may execute error checking and detect and correct errors in the configuration data based on the embedded error code.
1. An integrated circuit, comprising:
an array of configuration memory cells that configures the integrated circuit to implement a custom logic function, wherein a subset of the array of configuration memory cells are don't care memory cells that are spread out in the array, wherein a polarity change in one of the don't care bits preserves the functionality of the custom logic function, and wherein the don't care memory cells store an error code; and
error detection circuitry that detects whether the array of configuration memory cells exhibits an error based on the stored error code.
2. The integrated circuit of claim 1 , wherein the integrated circuit comprises a programmable integrated circuit.
3. The integrated circuit of claim 1 , wherein one of the don't care memory cells stores a row parity bit.
4. The integrated circuit of claim 1 , wherein one of the don't care memory cells stores a column parity bit.
5. The integrated circuit of claim 1 , wherein the error detection circuitry computes a parity bit for a group of the array of configuration memory cells, and wherein the group includes one of the don't care memory cells.
6. The integrated circuit of claim 5 , wherein the error detection circuitry further compares the computed parity bit to a bit stored at a given memory cell in the group.
7. The integrated circuit of claim 6 , wherein the given memory cell is another one of the don't care memory cells.
8. The integrated circuit of claim 5 , wherein the group of the array of memory cells comprises a row of configuration memory cells in the array.
9. The integrated circuit of claim 5 , wherein the group of the array of configuration memory cells comprises a column of configuration memory cells in the array.
10. A method of configuring an integrated circuit that includes an array of configuration memory cells, comprising:
identifying a subset of the array of configuration memory cells as don't care memory cells, wherein a polarity change in the don't care memory cells preserves the functionality of the integrated circuit;
computing a parity check bit for the array of memory cells; and
after identifying the subset of the array of configuration memory cells as don't care memory cells, storing the parity check bit in one of the don't care memory cells.
11. The method of claim 10 , wherein don't care memory cells are spread throughout the array.
12. The method of claim 10 , further comprising:
loading configuration data into configuration memory cells in the array other than the don't care memory cells.
13. The method of claim 10 , further comprising:
computing an error check bit for the array of memory cells; and
identifying an error by detecting a mismatch between the parity check bit and the error check bit.
14. The method of claim 10 , further comprising:
in response to detecting the mismatch, correcting the identified error.