Method and apparatus for performing automated timing closure analysis for systems implemented on target devices
View Patent ↗A method for generating a design for a system to be implemented on a target device includes compiling the design. Information used to make a compilation decision on the design is stored. A strategy to improve timing closure on a signal path on the design is derived using the information.
1. A method for generating a design for a system to be implemented on a target device, the method comprising:
storing information used for a compilation of the design;
deriving a strategy to improve timing closure on a signal path on the design using information stored that was used for a compilation of the design;
computing a score indicative of effectiveness of the strategy for improving the timing closure on the signal path, wherein the score is a function of an estimated amount of delay reduced by implementing the strategy and a required delay for the signal path; and
outputting the strategy with the score, wherein at least one of the storing, deriving, computing, and outputting is performed by a processor.
2. The method of claim 1 , wherein deriving the strategy comprises:
identifying an optimistic delay on the signal path from the information; and
identifying a number of level of logic to remove from the signal path for a realistic delay on the signal path to be less than or equal to the optimistic delay.
3. The method of claim 1 , wherein deriving the strategy comprises:
computing a first clock skew between a source node and sink node on the signal path, wherein clock signals are transmitted on a standard clock network;
computing a second clock skew between the source node and the sink node, wherein the clock signals are transmitted on a low-skew global clock network; and
transmitting the clock signals to the source node and the sink node on the low-skew global clock network if the first clock skew is greater than the second clock skew.
4. The method of claim 1 , wherein deriving the strategy comprises:
identifying a register on the signal path with slack imbalance; and
identifying a direction and number of logic levels to move the register to reduce the slack imbalance.
5. The method of claim 1 , wherein deriving the strategy comprises:
identifying a node on the signal path having a disallowed optimization; and
optimizing a subsequent compilation.
6. The method of claim 1 , wherein deriving the strategy comprises:
determining whether a first node and a second node on the signal path are placed in non-overlapping restricted regions; and
removing a requirement of having the first node and the second node placed in non-overlapping restricted regions in response to determining that the first node and the second node are placed beyond a tolerable distance.
7. The method of claim 1 , wherein deriving the strategy comprises:
determining whether the signal path crosses a partition boundary; and
removing the partition boundary in response to determining that the signal path crosses the partition boundary.
8. The method of claim 1 , wherein deriving the strategy comprises:
identifying a level of criticality assigned to the signal path during the compilation of the design from the information; and
assigning a higher level of criticality to the signal path on a subsequent compilation in response to determining that the level of criticality exceeds a threshold level.
9. The method of claim 1 , wherein deriving the strategy comprises:
determining whether a node on the signal path residing outside an area defined by a fanin node and a first fanout node has a second fanout node also residing outside the area; and
duplicating the node in response to determining that the node has the second fanout node also residing outside the area.
10. The method of claim 1 , wherein deriving the strategy comprises:
determining from the information whether a first node on the signal path placed in a first logic array block or second node on the signal path placed on a second logic array block were placed to improve density over performance; and
reducing logic utilization in the system in response to determining that either the first node or the second node was placed to improve density over performance.
11. The method of claim 1 , wherein deriving the strategy comprises:
comparing a delay on the signal path with an optimistic delay; and
reducing logic utilization in response to determining that the delay is greater than the optimistic delay.
12. The method of claim 1 , wherein computing the score comprises taking a minimum of a value 1 and [(an estimated amount of delay reduced by implementing the strategy)/(a required delay for the signal path)].
13. The method of claim 1 , wherein the score is a numerical value.
14. A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method comprising:
compiling a design of a system on a target device;
storing information used to make a compilation decision on the design;
deriving a strategy to improve timing closure on a signal path on the design using the information; and
computing a score indicative of effectiveness of the strategy for improving the timing closure on the signal path, wherein the score is a function of an estimated amount of delay reduced by implementing the strategy and a required delay for the signal path.
15. The non-transitory computer readable medium of claim 14 , wherein the information comprises placement constraints on nodes on the signal path.
16. The non-transitory computer readable medium of claim 14 , wherein the information comprises a level of criticality assigned to the signal path.
17. The non-transitory computer readable medium of claim 14 , wherein the information comprises an indication of whether a node on the signal path is placed on a building block on the target device that improves density at a cost of performance.
18. The non-transitory computer readable medium of claim 14 , wherein the information comprises an identity of an optimization disallowed for a node on the signal path and a reason for the disallowance.
19. The non-transitory computer readable medium of claim 14 , wherein the information comprises a maximum delay and minimum delay required for routing a signal on the signal path.
20. The non-transitory computer readable medium of claim 14 , wherein the information comprises an optimistic routing delay for the signal path.
21. The non-transitory computer readable medium of claim 14 , wherein compiling the design of the system comprises performing synthesis, placement, and routing of the design.
22. The non-transitory computer readable medium of claim 14 , wherein the score is a numerical value.
23. A system designer comprising:
a synthesis unit;
a placement unit;
a routing unit;
a storage unit operable to store information used to make a compilation decision on a design by at least one of the synthesis unit, placement unit, and routing unit; and
an analysis unit operable to derive a strategy to improve timing closure on a signal path on the design using the information and operable to compute a score indicative of effectiveness of the strategy for improving the timing closure on the signal path, wherein the score is a function of an estimated amount of delay reduced by implementing the strategy and a required delay for the signal path.
24. The system designer of claim 23 , wherein the analysis unit computes the score by taking a minimum of a value 1 and [(an estimated amount of delay reduced by implementing the strategy)/(a required delay for the signal path)].
25. The system designer of claim 23 further comprising a system designer manager operable to output the strategy with the score.
26. The system designer of claim 23 , wherein the score is a numerical value.