Multi-rate transceiver circuitry
View Patent ↗Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.
1. A method, comprising:
receiving a first reference clock signal at receiving circuitry, having a first frequency from external circuitry that is external to the receiving circuitry;
receiving a second reference clock signal at the receiving circuitry, having a second frequency from the external circuitry, wherein the second frequency is different from the first frequency;
determining a change in frequency a between the first frequency of the first reference clock signal and the second frequency of the second reference clock signal; and
in response to determining the change in frequency;
reconfiguring phase-locked loop (PLL) circuitry to generate a receiver clock signal for the receiving circuitry to match the second frequency; and
reconfiguring the receiving circuitry based at least in part on the receiver clock signal.
2. The method of claim 1 , wherein reconfiguring the receiving circuitry comprises:
reconfiguring the receiving circuitry from a first configuration to a second configuration; and
after reconfiguring the receiving, circuitry resetting the receiving circuitry.
3. The method of claim 1 , comprising receiving, using the receiving circuitry, a data stream associated with the second reference clock signal.
4. The method of claim 3 , wherein the data stream comprises a High Definition Multimedia Interface (HDMI) signal.
5. The method of claim 1 , comprising, in response to detecting the change in frequency, reconfiguring transmitting circuitry based at least in part on the receiver clock signal.
6. The method of claim 5 , comprising sequentially reconfiguring the transmitting circuitry and the receiving circuitry.
7. The method of claim 5 , comprising concurrently reconfiguring the transmitting circuitry and the receiving circuitry.
8. A circuitry comprising:
receiving circuitry configured to receive:
a first reference clock signal having a first frequency from external circuitry that is external to the circuitry; and
a second reference clock signal having a second frequency from the external circuitry, wherein the second frequency is different from the first frequency;
detector circuitry configured to detect a change in frequency between the first frequency of the first reference clock signal and the second frequency of the second reference clock signal; and
control circuitry configured to, in response to the detector circuitry detecting the change in frequency:
reconfigure phase-locked loop circuitry configured to generate a receiver clock signal having the second frequency; and
reconfigure the receiving circuitry operating at the first frequency to operate based at least in part on the receiver clock signal having the second frequency.
9. The circuitry of claim 8 , wherein the second reference clock signal is associated with a data stream, wherein the receiving circuitry is configured to receive the data stream.
10. The circuitry of claim 9 , wherein the data stream comprises video data.
11. The circuitry of claim 9 , wherein the data stream comprises a High Definition Multimedia Interface (HDMI) signal.
12. The circuitry of claim 8 , wherein the circuitry comprises an HDMI interface.
13. The circuitry of claim 8 , wherein the detector circuitry is configured to receive a single transition multimedia differential signaling (TMDS) clock signal as the second reference clock signal.
14. The circuitry of claim 8 , wherein the control circuitry is configured to, in response to the detector circuitry detecting the change in frequency:
generate a reconfiguration signal to reconfigure the receiving circuitry;
transmit the reconfiguration signal to the receiving circuitry;
generate a reset signal to reset the receiving circuitry; and
transmit the reset signal to the receiving circuitry.
15. The circuitry of claim 8 , wherein the circuitry is communicatively coupled to a transceiver, wherein the transceiver comprises the receiving circuitry.
16. The circuitry of claim 8 , wherein the control circuitry is configured to, in response to detecting the change in frequency, reconfigure transmitting circuitry to operate based at least in part on the receiver clock signal.
17. A circuitry comprising:
receiving circuitry configured to receive:
a first reference clock signal having a first frequency from external circuitry that is external to the circuitry; and
a second reference clock signal having a second frequency from the external circuitry, wherein the second frequency is different from the first frequency;
detector circuitry configured to receive the first reference clock signal and the second reference clock signal from the external circuitry and detect a change in frequency between the first frequency of the first reference clock signal and the second frequency of the second reference clock signal; and
control circuitry configured to, in response to the detector circuitry detecting the change in the frequency:
reconfigure clock generating circuitry configured to generate a transmitter clock signal based at least in part on the change in frequency; and
reconfigure transmitting circuitry based at least in part on the transmitter clock signal.
18. The circuitry of claim 17 , wherein the clock generating circuitry comprises phase-locked loop (PLL) circuitry.
19. The circuitry of claim 17 , wherein, in response to reconfiguring the transmitting transmitter circuitry to operate based at least in part on the transmitter clock signal, the transmitting circuitry is configured to transmit an output signal based at least in part on the transmitter clock signal.
20. The circuitry of claim 17 , wherein a field-programmable gate array comprises the circuitry.