Security variable scrambling
View Patent ↗Methods and systems are provided for securing an integrated circuit device against various security attacks, such as side-channel attacks. By limiting the number of different challenge vectors that can be combined with a critical variable of an encryption operation, it becomes more difficult to create enough side channel measurements to successfully perform statistical side-channel analysis.
1. A method for processing data based on a cryptographic operation, the method comprising:
scrambling, using scrambling circuitry, a secret value of a critical variable with a first element of a challenge vector, to generate a first scrambled value of the critical variable, wherein the critical variable is used in the cryptographic operation;
scrambling the first scrambled value of the critical variable with a second element of the challenge vector to generate a second scrambled value of the critical variable; and
encrypting the data based on the second scrambled value of the critical variable.
2. The method of claim 1 , wherein the challenge vector is one of an input to the cryptographic operation and an internal value of the cryptographic operation.
3. The method of claim 1 , wherein the challenge vector corresponds to one of an initialization vector (IV) and an internal counter.
4. The method of claim 1 , wherein the critical variable is one of an encryption key and an intermediate state corresponding to the cryptographic operation.
5. The method of claim 1 , wherein said scrambling the first scrambled value of the critical variable comprises:
conditionally combining the first scrambled value of the critical variable with a hidden mask variable, wherein the hidden mask variable is a function of a prior scrambled value of the critical variable.
6. The method of claim 5 , wherein the hidden mask variable is a combination of one or more internal encryption rounds, where one of the one or more internal encryption rounds uses the prior scrambled value of the critical variable.
7. The method of claim 1 , wherein the method is performed in a programmable logic device, and wherein the data being processed comprises a configuration bitstream.
8. The method of claim 1 , further comprising:
prior to scrambling the first scrambled value of the critical variable after decrypting a first data block, updating a hash vector based on a second data block.
9. The method of claim 8 , further comprising:
after decrypting the second data block, scrambling the scrambled value of the critical variable based on a second element of the hash vector to generate another scrambled value of the critical variable; and
decrypting a third data block based on the other scrambled value of the critical variable.
10. The method of claim 8 , wherein the critical variable is one of an encryption key and an intermediate state corresponding to the cryptographic operation.
11. The method of claim 8 , wherein said scrambling the first scrambled value of the critical variable comprises:
conditionally combining the first scrambled value of the critical variable with a hidden mask variable, wherein the hidden mask variable is a function of a prior scrambled value of the critical variable.
12. The method of claim 8 , wherein the method is performed in a programmable logic device, and wherein the data being processed comprises a configuration bitstream.
13. A system for processing data based on a cryptographic operation, the circuit comprising:
scrambling circuitry configured for:
scrambling a secret value of a critical variable with a first element of a challenge vector, to generate a first scrambled value of the critical variable, wherein the critical variable is used in the cryptographic operation, and
scrambling the first scrambled value of the critical variable with a second element of the challenge vector to generate a second scrambled value of the critical variable; and
encryption circuitry for encrypting the data based on the second scrambled value of the critical variable.
14. The system of claim 13 , wherein the challenge vector is one of an input to the cryptographic operation and an internal value of the cryptographic operation.
15. The system of claim 13 , wherein the challenge vector corresponds to one of an initialization vector (IV) and an internal counter.
16. The system of claim 13 , wherein the critical variable is one of an encryption key and an intermediate state corresponding to the cryptographic operation.
17. The system of claim 13 , wherein said scrambling circuitry is configured for conditionally combining the first scrambled value of the critical variable with a hidden mask variable, wherein the hidden mask variable is a function of a prior scrambled value of the critical variable.
18. The system of claim 17 , wherein the hidden mask variable is a combination of one or more internal encryption rounds, where one of the one or more internal encryption rounds uses the prior scrambled value of the critical variable.
19. The system of claim 13 , wherein the system comprises a programmable logic device, and wherein the data being processed comprises a configuration bitstream.