Behavioral simulation model for clock-data recovery phase-locked loop
View Patent ↗Method and non-transitory computer-readable medium storing instructions for simulating a phase-locked loop measures a first phase of a data signal and a second phase of a reference clock signal in a phase-locked loop to be simulated, filters the first phase of the data signal by a threshold function of a lock detection module of the phase-locked loop to be simulated, and adjusts the second phase of the reference clock signal to align with the filtered first phase of the data signal.
1. A method for simulating a phase-locked loop, the method comprising:
measuring a phase of a data signal and a phase of a reference clock signal in a phase-locked loop to be simulated;
filtering the phase of the data signal by a threshold function of a lock detection module that removes outliers of the data signal that exceed a threshold of the threshold function of the phase-locked loop to be simulated; and
adjusting the phase of the reference clock signal based on the data signal to align the phase of the reference clock signal with the filtered phase of the data signal.
2. The method of claim 1 , wherein the adjusting of the phase of the reference clock signal further comprises:
predicting an arrival time of a next data edge of the data signal based on a prediction model;
calculating a difference between an actual arrival time of the next data edge and the predicted arrival time of the next data edge;
determining whether the next data edge is valid based on the calculated difference; and
in response to determining that the next data edge is valid, updating the prediction model based on the calculated difference.
3. The method of claim 2 , further comprising notifying the lock detection module in response to determining that the next data edge is not valid.
4. The method of claim 1 , wherein the threshold function of the lock detection module emulates a low-pass filter.
5. The method of claim 1 , further comprising filtering the data signal and the reference clock signal to remove jitter and parts-per million (PPM) errors.
6. The method of claim 5 , wherein the jitter and the PPM errors are represented by a rounding-off error having an upper boundary, and wherein the threshold function of the lock detection module compares the rounding-off error with a threshold.
7. The method of claim 1 , further comprising:
calculating an amount of lag in the data signal with respect to the reference clock signal; and
applying a delay to the reference clock signal based on the calculated amount of lag.
8. The method of claim 7 , wherein the amount of lag is calculated during initialization of the phase-locked loop.
9. The method of claim 1 , further comprising implementing error conditions to simulate hardware behavior, wherein the error conditions include burst error, parts-per million (PPM) error, and accumulated error between data signal edges.
10. A programmable logic device configured as a phase-locked loop using a method of simulating the phase-locked loop, the programmable logic device being configured by:
measuring a phase of a data signal and a phase of a reference clock signal in a phase-locked loop to be simulated;
filtering the phase of the data signal by a threshold function of a lock detection module that removes outliers of the data signal that exceed a threshold of the threshold function of the phase-locked loop to be simulated; and
adjusting the phase of the reference clock signal based on the data signal to align the phase of the reference clock signal with the filtered phase of the data signal.
11. The programmable logic device of claim 10 , wherein, in the adjusting, the programmable logic device is configured by:
predicting an arrival time of a next data edge of the data signal based on a prediction model;
calculating a difference between an actual arrival time of the next data edge and the predicted arrival time of the next data edge;
determining whether the next data edge is valid based on the calculated difference; and
in response to determining that the next data edge is valid, updating the prediction model based on the calculated difference.
12. The programmable logic device of claim 11 , the programmable logic device being further configured by notifying the lock detection module in response to determining that the next data edge is not valid.
13. The programmable logic device of claim 10 , wherein the threshold function of the lock detection module emulates a low-pass filter.
14. The programmable logic device of claim 10 , the programmable logic device being further configured by filtering the data signal and the reference clock signal to remove jitter and parts-per million (PPM) errors.
15. The programmable logic device of claim 14 , wherein the jitter and the PPM errors are represented by a rounding-off error having an upper boundary, and wherein the threshold function of the lock detection module compares the rounding-off error with a threshold.
16. The programmable logic device of claim 10 , the programmable logic device being further configured by:
calculating an amount of lag in the data signal with respect to the reference clock signal; and
applying a delay to the reference clock signal based on the calculated amount of lag.
17. The programmable logic device of claim 16 , wherein the amount of lag is calculated during initialization of the phase-locked loop.
18. The programmable logic device of claim 10 , the programmable logic device being further configured by implementing error conditions to simulate hardware behavior, wherein the error conditions include burst error, parts-per million (PPM) error, and accumulated error between data signal edges.
19. A non-transitory computer-readable medium storing a plurality of instructions for simulating a phase-locked loop, the plurality of instructions comprising:
an instruction to measure a phase of a data signal and a phase of a reference clock signal in a phase-locked loop to be simulated;
an instruction to filter the phase of the data signal by a threshold function of a lock detection module that removes outliers of the data signal that exceed a threshold of the threshold function of the phase-locked loop to be simulated; and
an instruction to adjust the phase of the reference clock signal to align with the filtered phase of the data signal.
20. The non-transitory computer-readable medium of claim 19 , wherein the instruction that adjusts the phase of the reference clock signal further comprises:
an instruction to predict an arrival time of a next data edge of the data signal based on a prediction model;
an instruction to calculate a difference between an actual arrival time of the next data edge and the predicted arrival time of the next data edge;
an instruction to determine whether the next data edge is valid based on the calculated difference; and
an instruction to update the prediction model based on the calculated difference in response to the next data edge is determined to be valid.
21. The non-transitory computer-readable medium of claim 20 , wherein the plurality of instructions further comprises an instruction to notify the lock detection module in response to determining that the next data edge is not valid.
22. The non-transitory computer-readable medium of claim 19 , wherein the threshold function of the lock detection module emulates a low-pass filter.
23. The non-transitory computer-readable medium of claim 19 , wherein the plurality of instructions further comprises an instruction to filter the data signal and the reference clock signal to remove jitter and parts-per million (PPM) errors.
24. The non-transitory computer-readable medium of claim 23 , wherein the jitter and the PPM errors are represented by a rounding-off error having an upper boundary, and wherein the threshold function of the lock detection module compares the rounding-off error with a threshold.
25. The non-transitory computer-readable medium of claim 19 , wherein the plurality of instructions further comprises:
an instruction to calculate an amount of lag in the data signal with respect to the reference clock signal; and
an instruction to apply a delay to the reference clock signal based on the calculated amount of lag.
26. The non-transitory computer-readable medium of claim 25 , wherein the amount of lag is calculated during initialization of the phase-locked loop.
27. The non-transitory computer-readable medium of claim 19 , wherein the plurality of instructions further comprises an instruction to implement error conditions to simulate hardware behavior, wherein the error conditions include burst error, parts-per million (PPM) error, and accumulated error between data signal edges.