Pipelined scan structures for testing embedded cores
View Patent ↗A scan testing technique in which test data is pipelined to scan logic within an integrated circuit. In system on a programmable chip (SOPC) designs, pipelines are easily built in the programmable logic device (PLD) logic by configuring programmable interconnects to connect registers in a pipelined manner so that test data can be pipelined to scan the logic under test. In system on a chip (SOC) designs, a smart test generator-analyzer is configured to recursively extract pipeline information from a design-so that test data can be pipelined to scan the logic under test. Generally, test data is pipelined using existing functional logic and/or scan chains. Furthermore, a failure analysis (FA) platform is described. The FA platform is operable to take as its input a failing vector as well as a pipelined scan vector and unroll the pipeline sequence to determine which vector caused the failure.
1. A method for scan testing logic within an integrated circuit, the method comprising:
shifting input test data into multiple input-side scan chains in parallel, wherein at least two input-side scan chains are on different levels of a pipeline;
applying the input test data from the multiple input-side scan chains to the logic under test;
capturing output test data from the logic under test into multiple output-side scan chains, wherein at least two output-side scan chains are on different levels of the pipeline, the output test data being the result of the input test data being applied to the logic under test; and
shifting the output test data out from the multiple output-side scan chains in parallel.
2. The method of claim 1 , wherein the input-side scan chains on different pipeline levels are interconnected.
3. The method of claim 2 , wherein the output-side scan chains on different pipeline levels are interconnected.
4. The method of claim 3 , wherein each of the input-side and output-side scan chains comprises a plurality of registers.
5. The method of claim 4 , wherein at least one input-side or output-side scan chain is associated with another logic within the integrated circuit that is not in the scan path.
6. The method of claim 4 , wherein at least one input-side or output-side scan chain share a pair of access ports.
7. The method of claim 4 , wherein the plurality of registers of an input-side scan chain and an output-side scan chain are part of a common scan chain.
8. The method of claim 4 , wherein either applying the input test data from the multiple input-side scan chains to the logic under test or capturing output test data out from the logic under test in multiple output-side scan chains comprises:
shifting test data synchronously on a clock cycle.
9. The method of claim 8 , wherein either applying the input test data from the multiple input-side scan chains to the logic under test or capturing output test data out from the logic under test in multiple output-side scan chains comprises:
shifting test data in unison.
10. The method of claim 9 , wherein either applying the input test data from the multiple input-side scan chains to the logic under test or capturing output test data out from the logic under test in multiple output-side scan chains comprises:
shifting test data between scan chains.
11. The method of claim 10 , wherein either applying the input test data from the multiple input-side scan chains to the logic under test or capturing output test data out from the logic under test in multiple output-side scan chains comprises:
shifting test data between registers.
12. The method of claim 1 , wherein applying the input test data from the multiple input-side scan chains to the logic under test comprises:
applying at least a portion of the input test data through a first logic different from the logic under test.
13. The method of claim 12 , wherein capturing the output test data from the logic under test in multiple output-side scan chains comprises:
applying at least a portion of the output test data through a second logic different from the logic under test.
14. The method of claim 1 , further comprising:
extracting pipeline information from the integrated circuit to identify the multiple input-side and output-side scan chains associated with the logic under test.
15. The method of claim 1 , wherein the integrated circuit is implemented in either an ASIC or an ASSP.
16. The method of claim 1 , wherein the integrated circuit is implemented in a programmable device.
17. The method of claim 16 , wherein the logic under test is an embedded core.
18. The method of claim 16 , further comprising:
constructing the multiple input-side and output-side scan chains with programmable logic and interconnects in the programmable logic device.
19. A method for scan testing logic within an integrated circuit, the method comprising:
shifting input test data into multiple input-side scan chains in parallel, wherein at least two input-side scan chains are on different levels of a pipeline;
applying the input test data from the multiple input-side scan chains to the logic under test;
capturing output test data from the logic under test in multiple output-side scan chains, wherein at least two output-side scan chains are on different levels of the pipeline, the output test data being the result of the input test data being applied to the logic under test;
shifting the output test data out from the multiple output-side scan chains in parallel; and
extracting pipeline information from the integrated circuit to account for translation of test data through logic other than the logic under test.
20. An integrated circuit having logic for scan testing, comprising:
a logic under test;
a plurality of input-side scan chains operable to receive input test data in parallel and to make available the input test data for applying to the logic under test, wherein at least two input-side scan chains are on different levels of a pipeline; and
a plurality of output-side scan chains operable to receive output test data from the logic under test and to make available the output test data for observation from the output-side scan chains in parallel, wherein at least two output-side scan chains are on different levels of the pipeline.
21. The integrated circuit of claim 20 , further comprising:
a plurality of interconnects for connecting the multiple input-side scan chains and the multiple output-side scan chains to the logic under test.
22. The integrated circuit of claim 21 , wherein each input-side and output-side scan chain comprises a plurality of registers.
23. The integrated circuit of claim 22 , wherein at least one input-side or output-side scan chain is associated with another logic within the integrated circuit that is not in the scan path.
24. The integrated circuit of claim 22 , wherein at least one input-side or output-side scan chain share a pair of access ports.
25. The integrated circuit of claim 20 , wherein the integrated circuit is implemented in either an ASIC or an ASSP.
26. The integrated circuit of claim 20 , wherein the integrated circuit is implemented in a programmable device.
27. The integrated circuit of claim 26 , wherein the logic under test is an embedded core.
28. The integrated circuit of claim 20 , wherein the input test data comprises multiple input test data vectors and the output test data comprises multiple output test data vectors.