Multiplier operable to perform a variety of operations
View Patent ↗Methods and apparatus are provided for implementing circuitry operable to perform barrel shifting, multiplication, and rotation operations in hard coded logic on a programmable chip. A hard coded multiplier is augmented using multiplexer circuitry, a logical operation, and a bypassable 2^N functional block. Based on control signals, the multiplexer circuitry can be used to select a rotation, multiplication, or barrel shifted output. Multiplexer control signals also provide sign information associated with operands passed to the multiplier. A single augmented multiplier can perform barrel shifting, rotation, or multiplication operations. Inputs of a multiplier can also be selectively grounded to allow the multiplier to perform logic operations.
1. A programmable chip, comprising:
a plurality of programmable logic elements;
a hard-coded multiplier implemented using only AND gates and adders, the hard-coded multiplier configured to receive a first operand over a plurality of first operand input lines and a second operand over a plurality of second operand input lines and to provide a first output over a plurality of first output lines, wherein the plurality of first operand input lines and the plurality of second operand input lines are all inputs to the hard-coded multiplier,
wherein a subset of the plurality of first operand input lines and a subset of the second plurality of input lines are grounded such that the hard-coded multiplier provides only two-input logic operations on a subset of the first plurality of output lines,
wherein the hard-coded multiplier uses hard-coded logic to perform shifting, rotation, and multiplication operations in addition to hard-coded two-input logic operations, and wherein a subset of the plurality of output lines provides a plurality of XOR and non-XOR functions.
2. The programmable chip of claim 1 , wherein the multiplier is a 9×9 multiplier.
3. The programmable chip of claim 2 , wherein the plurality of first operand input lines includes lines A 0 , A 1 , A 2 , A 3 , A 4 , A 5 , A 6 , A 7 , and A 8 .
4. The programmable chip of claim 3 , wherein the subset of the plurality of first operand input lines that are grounded include lines A 1 , A 3 , A 5 , and A 7 .
5. The programmable chip of claim 4 , wherein the plurality of second operand input lines includes lines B 0 , B 1 , B 2 , B 3 , B 4 , B 5 , B 6 , B 7 , and B 8 .
6. The programmable chip of claim 5 , wherein the subset of the plurality of second operand input lines that are grounded include lines B 1 , B 3 , B 5 , and B 7 .
7. The programmable chip of claim 6 , wherein the plurality of first output lines includes lines CO, C 1 , C 2 , C 3 , C 4 , C 5 , C 6 , C 7 , C 8 , C 9 , C 10 , CII, C 12 , C 13 , C 14 , C 15 , C 16 , and C 17 .
8. The programmable chip of claim 7 , wherein CO=A 0 AND B 0 , C 12 =A 6 AND B 6 , and C 16 =A 8 AND B 8 .
9. The programmable chip of claim 8 , wherein C 2 =A 0 AND B 2 +A 2 AND B 0 and C 14 =A 6 AND B 8 +A 8 AND B 6 .
10. A system, comprising:
a plurality of programmable logic elements;
a hard-coded multiplier implemented using only AND gates and adders, the hard-coded multiplier configured to receive a first operand over a plurality of first operand input lines and a second operand over a plurality of second operand input lines and to provide a first output over a plurality of first output lines, wherein the plurality of first operand input lines and the plurality of second operand input lines are all inputs to the hard-coded multiplier,
wherein a subset of the plurality of first operand input lines and a subset of the second plurality of input lines are grounded such that the hard-coded multiplier provides only two-input logic operations on a subset of the first plurality of output lines, and
wherein the hard-coded multiplier uses hard-coded logic to perform shifting, rotation, and multiplication operations in addition to hard-coded two-input logic operations, and wherein a subset of the plurality of output lines provides a plurality of XOR and non-XOR functions.
11. The system of claim 10 , wherein the multiplier is a 9×9 multiplier.
12. The system of claim 11 , wherein the plurality of first operand input lines includes lines A 0 , A 1 , A 2 , A 3 , A 4 , A 5 , A 6 , A 7 , and A 8 .
13. The system of claim 12 , wherein the subset of the plurality of first operand input lines that are grounded include lines A 1 , A 3 , A 5 , and A 7 .
14. The system of claim 13 , wherein the plurality of second operand input lines includes lines B 0 , B 1 , B 2 , B 3 , B 4 , B 5 , B 6 , B 7 , and B 8 .
15. The system of claim 14 , wherein the subset of the plurality of second operand input lines that are grounded include lines B 1 , B 3 , B 5 , and B 7 .
16. The system of claim 15 , wherein the plurality of first output lines includes lines CO, C 1 , C 2 , C 3 , C 4 , C 5 , C 6 , C 7 , C 8 , C 9 , C 10 , CII, C 12 , C 13 , C 14 , C 15 , C 16 , and C 17 .
17. The system of claim 16 , wherein CO=A 0 AND B 0 , C 12 =A 6 AND B 6 , and C 16 =A 8 AND B 8 .
18. The system of claim 17 , wherein C 2 =A 0 AND B 2 +A 2 AND B 0 and C 14 =A 6 AND B 8 +A 8 AND B 6 .
19. A hard-coded multiplier comprising:
means to receive a first operand over a plurality of first operand input lines and a second operand over a plurality of second operand input lines, wherein the plurality of first operand input lines and the plurality of second operand input lines are all inputs to the hard-coded multiplier;
means to provide a first output over a plurality of first output lines, wherein a subset of the plurality of first operand input lines and a subset of the second plurality of input lines are grounded such that the hard-coded multiplier provides only two-input logic operations on a subset of the first plurality of output lines,
wherein the hard-coded multiplier implemented using only AND gates and adders uses hard-coded logic to perform shifting, rotation, and multiplication operations in addition to hard-coded two-input logic operations, and wherein a subset of the plurality of first output lines provides a plurality of XOR and non-XOR functions.
20. The hard-coded multiplier of claim 19 , wherein the multiplier is a 9×9 multiplier.