Forward error correction with configurable latency
View Patent ↗A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target Bit Error Rate (BER) against an actual BER and adjusts the size of a configurable buffer such that the target BER may be achieved when utilizing the smallest buffer size possible. When errors are corrected without the utilization of each of the configurable buffer locations, the algorithm reduces the size of the buffer by y buffer locations; the algorithm may continue to successively reduce the size of said buffer until the minimum number of buffer locations are utilized to achieve the target BER. If the buffer locations have been reduced such that the buffer size is too small and the target BER cannot be achieved, the algorithm may increase the size of the buffer until the minimum number of buffer locations are utilized to achieve the target BER.
1. A method of performing forward error correction with configurable latency, comprising:
(a) a plurality of data input to a transmission system, wherein said data includes a target bit error rate;
(b) a configurable size buffer with a plurality of buffer locations, wherein a forward error correction code corrects said data as said data is transmitted through said buffer;
(c) an error monitor to evaluate an actual bit error rate of said data output from said configurable size buffer; and
(d) a configurable latency algorithm, wherein said algorithm begins by utilizing the maximum number of available buffer locations to achieve said target bit error rate, and said algorithm then reduces the size of said buffer by y buffer locations when errors are corrected without the utilization of each of said buffer locations, whereby said algorithm may continue to successively reduce the size of said buffer until the minimum number of said buffer locations are utilized to achieve said target bit error rate or, where said buffer locations have been reduced such that said buffer size is too small and said target bit error rate cannot be achieved, said algorithm may increase the size of said buffer until the minimum number of said buffer locations are utilized to achieve said target bit error rate.
2. The method of claim 1 , wherein said forward error correction code is a Bose Ray-Chaudhuri (BCH) code.
3. The method of claim 2 , wherein said Bose Ray-Chaudhuri (BCH) code is a BCH (1023, 993) parent code, shortened to a BCH (1000, 970) code.
4. The method of claim 1 , wherein x=y or x≠y.