IP Library Granted Patent US 7,536,579
Granted Patent B2
US 7,536,579 · App. 11/462,157 · Granted May 19, 2009

Skew-correcting apparatus using iterative approach

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Quick Facts
Patent No.
US 7,536,579
App. No.
11/462,157
Granted
May 19, 2009
Kind
B2
Abstract

An apparatus for determining the amount of skew to be injected for system skew compensation in a high-speed data communications system including a plurality of lanes with a data bus per lane. Such skew compensation is necessary due to inherent system skew. By iterating through the possible intervals within the maximum expected skew search space, the correct combination of search space intervals for all lanes can be determined to provide alignment and thus compliancy with relevant standards, such as the SFI-5 and SxI-5 standards, in terms of data skew specifications.

Claims (11)

1. A skew detection apparatus for detecting the amount of skew in at least one of a plurality of transmitting lanes, in relation to a reference lane, of a parallel data transmission system, comprising:

(a) a plurality of transmitting lane pairs with one of a plurality of transceivers for each of said plurality of transmitting lane pairs, said plurality of transceivers comprising a transmitter and a receiver, wherein one of said plurality of transmitting lane pairs is a reference lane and one of said plurality of transceivers is a reference transceiver; and

(b) one or more of a plurality of feedback signals, wherein one or more of said plurality of transmitting lane pairs are coupled at said transmitters to one or more of a plurality of status signals at said receivers via said plurality of feedback signals; and

(c) an amount of skew in at least one of said plurality of transmitting lane pairs, wherein said amount of skew is determined by a iterative process, said iterative process comprising a algorithm which is implemented to systematically iterate through a plurality of skew injection parameters for each of said plurality of transmitting lane pairs to identify one or more offsetting skew amounts to be injected into any of said plurality of transmitting lane pairs, at the transmit side of a circuit, to re-align said plurality of transmitting lane pairs and achieve transmission lane alignment.

2. The apparatus of claim 1 , wherein said plurality of feedback signals are associated with one of said plurality of transmitting lane pairs, one or more groups of said plurality of transmitting lane pairs, or a aggregate signal of all of said plurality of transmitting lane pairs.

3. The apparatus claim 1 , wherein said plurality of feedback signals report the successful, error-free reception of a data stream from at least one of said receivers to at least one said transmitters.

4. A skew correction apparatus for correcting the amount of skew in at least one of a plurality of transmitting lanes, in relation to a reference lane, of a parallel data transmission system, comprising:

(a) a plurality of transmitting lane pairs with one of a plurality of transceivers for each of said plurality of transmitting lane pairs, said plurality of transceivers comprising a transmitter and a receiver, wherein one of said plurality of transmitting lane pairs is a reference lane and one of said plurality of transceivers is a reference transceiver; and

(b) a buffer to delay said plurality of transmitting lane pairs by a Unit Interval of Time (UI); and

(c) a offset to said buffer with information on an amount of skew in at least one of said plurality of transmitting lane pairs, wherein said amount of skew is determined by a iterative process, said iterative process comprising a algorithm which is implemented to systematically iterate through a plurality of skew injection parameters for each of said plurality of transmitting lane pairs, thereby indicting a offsetting skew amount to be injected into any of said plurality of transmitting lane pairs, at the transmit side of a circuit, to re-align said plurality of transmitting lane pairs and achieve transmission lane alignment.

5. The apparatus of claim 4 , wherein said buffer is a First-In-First-Out (FIFO) buffer.

Assignments (9)
CHANGE OF NAME Recorded Oct 10, 2022
From: INTEL TECHNOLOGY OF CANADA, LTD.
To: INTEL TECHNOLOGY OF CANADA, ULC
Reel/Frame 061359/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2022
From: INTEL TECHNOLOGY OF CANADA, ULC
To: INTEL CORPORATION
Reel/Frame 061368/0947 →
CHANGE OF NAME Recorded Aug 29, 2022
From: INTEL OF CANADA, LTD.
To: INTEL TECHNOLOGY OF CANADA, LTD.
Reel/Frame 061334/0500 →
MERGER AND CHANGE OF NAME Recorded Aug 29, 2022
From: ALTERA CANADA LTD.; INTEL OF CANADA, LTD.
To: INTEL OF CANADA, LTD.
Reel/Frame 060921/0206 →
CHANGE OF NAME Recorded Aug 29, 2022
From: ALTERA CANADA CO.
To: ALTERA CANADA LTD.
Reel/Frame 061333/0007 →
CHANGE OF NAME Recorded Jan 9, 2012
From: ALTERA NEWFOUNDLAND TECHNOLOGY CORP.
To: ALTERA CANADA CO.
Reel/Frame 027500/0519 →
CHANGE OF NAME Recorded Apr 26, 2011
From: AVALON MICROELECTONICS INC.
To: ALTERA NEWFOUNDLAND TECHNOLOGY CORP.
Reel/Frame 026181/0242 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2008
From: HAAS, WALLY; PITTMAN, MUTEMA JOHN; RUMBOLT, CHUCK
To: AVALON MICROELECTRONICS, INC.
Reel/Frame 021542/0084 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2007
From: HAAS, WALLY; PITTMAN, MUTEMA JOHN; RUMBOLT, CHUCK
To: AVALON MICROELECTRONICS, INC.
Reel/Frame 020177/0266 →