Skew-correcting apparatus using dual loopback
View Patent ↗An apparatus for determining the amount of skew injected into a high-speed data communications system, including a plurality of lanes having a data bus per lane, relative to a reference lane, for system skew compensation. By knowing the relative amount of skew that each lane requires for alignment, an appropriate amount of skew is then injected on each lane to provide alignment and thus compliancy with the SFI-5 and SxI-5 standards, in terms of data skew specifications. The relative skew amounts for each transmitting lane are determined using dual loopback methods.
1. A skew detection apparatus for detecting the amount of skew in at least one of a plurality of transmitting lanes, in relation to a reference lane, of a parallel data transmission system, comprising:
(a) one of a plurality of transceivers coupled to one of said plurality of transmitting lane pairs, one of said plurality of transceivers comprising a transmitter and a receiver, wherein one of said plurality of transmitting lane pairs is a reference lane and one of said plurality of transceivers is a reference transceiver;
(b) a dual loopback coupled from one or more outputs from said transmitter to one or more inputs of said receiver via a multiplexer, wherein said multiplexer selects data from a plurality of data, said plurality of data comprising regular data and a plurality of loopback data, wherein said multiplexer selects one of said plurality of data, whereby any other of said plurality of data can subsequently be selected by said multiplexer to change from one of said plurality of data to any other of said plurality of data; and
(c) a logic circuit to implement an equation to detect an amount of skew in at least one of said plurality of transmitting lane pairs through said plurality of loopback data, whereby said amount of skew indicates offsetting skew to be injected into any of said plurality of transmitting lane pairs, at the transmit side of a circuit, to re-align said plurality of transmitting lane pairs and achieve transmission lane alignment.
2. The apparatus of claim 1 , wherein said reference lane and said reference transceiver are chosen from said plurality of transmitting lane pairs and said plurality of transceivers, or said reference lane and said reference transceiver are provided in addition to said plurality of transmitting lane pairs and said plurality of transceivers for the purpose of providing said reference lane to said plurality of transmitting lane pairs and said reference transceiver to said plurality of transceivers.
3. The apparatus of claim 1 , wherein dual loopback is achieved by using said plurality of loopback data, said plurality of loopback data comprising internal loopback and external loopback for each of said plurality of transceivers, wherein dual loopback to said reference lane and said reference transceiver may or may not be implemented.
4. The apparatus of claim 1 , wherein dual loopback is achieved by using external loopback for each of said plurality of transceivers, wherein dual loopback to said reference lane and said reference transceiver may or may not be implemented.
5. The apparatus of claim 1 , wherein dual loopback is achieved by using internal loopback for each of said plurality of transceivers, wherein dual loopback to said reference lane and said reference transceiver may or may not be implemented.
6. The apparatus of claim 1 , wherein internal loopback is selected by said plurality of transceivers, said plurality of data being selectable by said plurality of transceivers to achieve dual loopback.
7. The apparatus of claim 1 , wherein external loopback is selected by a plurality of external circuitry elements, said plurality of data being selectable by said plurality of external circuitry elements to achieve dual loopback.
8. The apparatus of claim 7 , wherein said external circuitry elements is a second multiplexer, said second multiplexer comprising: at least one of a plurality of inputs for said plurality of transmitting lane pairs, wherein said plurality of transmitting lane pairs are used for external loopback; at least one of a plurality of inputs for said plurality of transmitting lane pairs, wherein said plurality of transmitting lane pairs are used for regular data; and at least one of a plurality of outputs to a receive terminal of one of said plurality of transceivers, wherein said plurality of transceivers may or may not include said reference transceiver.
9. The apparatus of claim 1 , wherein a plurality of internal skew constants comprising internal skew from internal loopback between said plurality of transceivers and within said plurality of transceivers, wherein said plurality of transceivers may or may not include said reference transceiver, are determined through empirical information determined through a mode of empirical testing, wherein said mode of empirical testing is a training sequence.
10. The apparatus of claim 1 , wherein a plurality of external skew constants comprising external skew from external loopback between said plurality of transceivers, wherein said plurality of transceivers may or may not include said reference transceiver, are determined through empirical information determined through said mode of empirical testing, wherein said mode of empirical testing is said training sequence.
11. The apparatus of claim 1 , wherein said empirical information is determined by said mode of empirical testing, wherein said mode of empirical testing is said training sequence, wherein said training sequence is a Pseudo-Random Bit Sequence (PRBS) pattern.
12. A skew correction apparatus for detecting and correcting the amount of skew in at least one of a plurality of transmitting lanes, in relation to a reference lane, of a parallel data transmission system, comprising:
(a) one of a plurality of transceivers coupled to one of said plurality of transmitting lane pairs, one of said plurality of transceivers comprising a transmitter and a receiver, wherein one of said plurality of transmitting lane pairs is a reference lane and one of said plurality of transceivers is a reference transceiver;
(b) a buffer to delay said plurality of transmitting lane pairs by a Unit Interval of Time (UI); and
(c) a logic circuit to implement an equation to detect an amount of skew in at least one of said plurality of transmitting lane pairs through a plurality of loopback data, whereby said amount of skew indicates to said buffer the offsetting skew to be injected into any of said plurality of transmitting lane pairs, at the transmit side of a circuit, to re-align said plurality of transmitting lane pairs and achieve transmission lane alignment.
13. The apparatus of claim 12 , wherein said reference lane and said reference transceiver are chosen from said plurality of transmitting lane pairs and said plurality of transceivers, or said reference lane and said reference transceiver are provided in addition to said plurality of transmitting lane pairs and said plurality of transceivers for the purpose of providing said reference lane to said plurality of transmitting lane pairs and said reference transceiver to said plurality of transceivers.
14. The apparatus of claim 12 , wherein said buffer is a First-In-First-Out (FIFO) buffer.