Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein
View Patent ↗A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a switch on a semiconductor substrate, and forming a driver switch of a driver embodied in a transistor. The method of forming the transistor includes forming a gate over the semiconductor substrate. The method of forming the transistor also includes forming a source/drain by forming a lightly doped region adjacent a channel region recessed into the semiconductor substrate, and forming a heavily doped region adjacent the lightly doped region. The method of forming the transistor further includes forming an oppositely doped well under and within the channel region. The method of forming the transistor still further includes forming a doped region with a doping concentration profile less than the heavily doped region between the heavily doped region and the oppositely doped well.
1. A method of forming an integrated circuit, comprising:
providing a semiconductor substrate;
forming a switch on said semiconductor substrate; and
forming a driver switch of a driver embodied in a transistor, including:
forming a gate over said semiconductor substrate,
forming a source/drain by:
forming a lightly doped region adjacent a channel region recessed into said semiconductor substrate, and
forming a heavily doped region of like type to and adjacent said lightly doped region,
forming an oppositely doped well with respect to said lightly and heavily doped regions under and within said channel region,
forming a doped region of like type to said heavily doped region and between said heavily doped region and said oppositely doped well, said doped region having a doping concentration profile less than a doping concentration profile of said heavily doped region, and
forming an oppositely doped buried layer with respect to and under said doped region.
2. The method as recited in claim 1 wherein said switch is a transistor and forming said switch embodied in said transistor, includes:
forming a gate over said semiconductor substrate,
forming a source/drain by:
forming a lightly doped region adjacent a channel region recessed into said semiconductor substrate, and
forming a heavily doped region adjacent said lightly doped region, and
forming an oppositely doped well with respect to said lightly and heavily doped regions under and within said channel region.
3. The method as recited in claim 2 wherein forming said switch embodied in said transistor further includes forming a doped region between said heavily doped region and said oppositely doped well, said doped region having a doping concentration profile less than a doping concentration profile of said heavily doped region.
4. The method as recited in claim 1 wherein forming said transistor, further includes:
forming another source/drain by:
forming a lightly doped region adjacent said channel region, and
forming a heavily doped region adjacent said lightly doped region, and
forming another doped region between said heavily doped region of said another source/drain and said oppositely doped well, said another doped region having a doping concentration profile less than a doping concentration profile of said heavily doped region of said another source/drain.
5. The method as recited in claim 1 wherein forming said transistor, further includes:
forming a gate dielectric layer over said semiconductor substrate, and
forming gate sidewall spacers about said gate.
6. The method as recited in claim 1 wherein forming said transistor, further includes:
forming a salicide layer over said gate and said source/drain, and
forming metal contacts over said salicide layer.
7. The method as recited in claim 1 wherein said transistor is a laterally diffused metal oxide semiconductor device.
8. The method as recited in claim 1 wherein said heavily doped region is adjacent to but not surrounded by said lightly doped region.
9. The method as recited in claim 1 further comprising forming a shallow trench isolation region within said semicouductor substrate.
10. The method as recited in claim 1 further comprising forming a complementary metal oxide semiconductor device on said semiconductor substrate including forming a source/drain having a heavily doped region with a doping concentration profile different from said doping concentration profile of said heavily doped region of said source/drain of said transistor.
11. A method of forming an integrated circuit, comprising:
providing a semiconductor substrate;
forming a switch on a semiconductor substrate:
forming a driver switch of a driver embodied in a laterally diffused metal oxide semiconductor device, including:
forming a gate over said semiconductor substrate,
forming a source/drain by:
forming a lightly doped region adjacent a channel region recessed into said semiconductor substrate, and
forming a heavily doped region of like type to and adjacent to but not surrounded by said lightly doped region,
forming an oppositely doped well with respect to said lightly and heavily doped regions under and within said channel region, and
forming a doped region of like type to said heavily doped region and between said heavily doped region and said oppositely doped well, said doped region having a doping concentration profile less than a doping concentration profile of said heavily doped region; and
forming a complementary metal oxide semiconductor device on said semiconductor substrate.
12. The method as recited in claim 11 wherein said switch is a transistor and forming said switch embodied in said transistor, includes:
forming a gate over said semiconductor substrate,
forming a source/drain by:
forming a lightly doped region adjacent a channel region recessed into said semiconductor substrate, and
forming a heavily doped region adjacent said lightly doped region, and
forming an oppositely doped well with respect to said lightly and heavily doped regions under and within said channel region.
13. The method as recited in claim 12 wherein forming said switch embodied in said transistor further includes forming a doped region between said heavily doped region and said oppositely doped well, said doped region having a doping concentration profile less than a doping concentration profile of said heavily doped region.
14. The method as recited in claim 11 wherein forming said laterally diffused metal oxide semiconductor device, further includes:
forming another source/drain by:
forming a lightly doped region adjacent said channel region, and
forming a heavily doped region adjacent said lightly doped region, and
forming another doped region between said heavily doped region of said another source/drain and said oppositely doped well, said another doped region having a doping concentration profile less than a doping concentration profile of said heavily doped region of said another source/drain.
15. The method as recited in claim 11 wherein forming said laterally diffused metal oxide semiconductor device, further includes:
forming a gate dielectric layer over said semiconductor substrate; and
forming gate sidewall spacers about said gate.
16. The method as recited in claim 11 wherein forming said laterally diffused metal oxide semiconductor device, further includes:
forming a salicide layer over said gate and said source/drain, and
forming metal contacts over said salicide layer.
17. The method as recited in claim 11 wherein said laterally diffused metal oxide semiconductor device is a P-type laterally diffused metal oxide semiconductor device.
18. The method as recited in claim 11 further comprising forming an oppositely doped buried layer within said semiconductor substrate.
19. The method as recited in claim 11 further comprising forming a shallow trench isolation region within said semiconductor substrate.
20. The method as recited in claim 11 wherein forming said complementary metal oxide semiconductor device includes forming a source/drain having a heavily doped region with a doping concentration profile different from said doping concentration profile of said heavily doped region of said source/drain of said laterally diffused metal oxide semiconductor device.