IP Library › Granted Patent US 10,643,971
Granted Patent B2
US 10,643,971 · App. 16/542,247 · Granted May 5, 2020

Method for fabricating a semiconductor and semiconductor package

Inventors: Gottfried Beer (Nittendorf, DE); Irmgard Escher-Poeppel (Regensburg, DE)
Assignee: Intel Deutschland GMBH
H01L24/96H01L21/561H01L21/565H01L21/568H01L21/76879H01L23/3128H01L24/18H01L24/19H01L24/97H01L2224/04105H01L2224/12105H01L2224/18H01L2224/2919H01L2224/83856H01L2224/92144H01L2224/97H01L2924/014H01L2924/01005H01L2924/01006H01L2924/01013H01L2924/01029H01L2924/01033H01L2924/01068H01L2924/01075H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/12042H01L2924/12044H01L2924/14H01L2924/1461H01L2924/181
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,643,971
App. No.
16/542,247
Granted
May 5, 2020
Kind
B2
Abstract

A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

Claims (41)

1. A semiconductor chip package, comprising:

a semiconductor chip having a front surface and a back surface opposite the front surface, and the semiconductor chip having side surfaces between the front surface and the back surface;

a contact pad on the front surface of the semiconductor chip;

a mold material layer on the back surface and side surfaces of the semiconductor chip, the mold material layer having a front surface and a back surface opposite the front surface, and the mold material layer having side surfaces between the front surface and the back surface, wherein the front surface of the mold material layer is co-planar with the front surface of the semiconductor chip;

a dielectric layer on the front surface of the mold material and on the front surface of the semiconductor chip, the dielectric layer having side surfaces in vertical alignment with the side surfaces of the mold material layer;

an electrical conductor in the dielectric layer, the electrical conductor in contact with the contact pad, and the electrical conductor having a width; and

a conductive contact area in the dielectric layer, the conductive contact area in contact with the electrical conductor, the electrical contact area having a width greater than a width of the electrical conductor, and the conductive contact area having a surface co-planar with the dielectric layer.

2. The semiconductor chip package of claim 1 , wherein the dielectric layer comprises an additive.

3. The semiconductor chip package of claim 1 , wherein the mold material layer comprises an aliphatic polymer.

4. The semiconductor chip package of claim 1 , wherein the mold material layer comprises an aromatic polymer.

5. The semiconductor chip package of claim 1 , wherein the mold material layer comprises a thermoplastic polymer.

6. The semiconductor chip package of claim 1 , wherein the mold material layer comprises a thermoset polymer.

7. A semiconductor chip package, comprising:

a semiconductor chip having a front surface and a back surface opposite the front surface, and the semiconductor chip having side surfaces between the front surface and the back surface;

a contact pad on the front surface of the semiconductor chip;

a mold material layer on the back surface and side surfaces of the semiconductor chip, the mold material layer having a front surface and a back surface opposite the front surface, and the mold material layer having side surfaces between the front surface and the back surface, wherein the front surface of the mold material layer is co-planar with the front surface of the semiconductor chip;

a material layer on the front surface of the mold material and on the front surface of the semiconductor chip, the material layer having side surfaces in vertical alignment with the side surfaces of the mold material layer;

a seed layer on the material layer;

an electrical conductor in the material layer and in the seed layer, the electrical conductor in contact with the contact pad, and the electrical conductor having a width; and

a conductive contact area in contact with the electrical conductor and the seed layer, the electrical contact area having a width greater than a width of the electrical conductor, and the conductive contact area having side surfaces vertically aligned with side surfaces of the seed layer.

8. The semiconductor chip package of claim 7 , wherein the material layer comprises a preimpregnated foil.

9. The semiconductor chip package of claim 7 , wherein the seed layer comprises titanium and copper.

10. The semiconductor chip package of claim 7 , wherein the mold material layer comprises an aliphatic polymer.

11. The semiconductor chip package of claim 7 , wherein the mold material layer comprises an aromatic polymer.

12. The semiconductor chip package of claim 7 , wherein the mold material layer comprises a thermoplastic polymer.

13. The semiconductor chip package of claim 7 , wherein the mold material layer comprises a thermoset polymer.

14. A semiconductor chip package, comprising:

a semiconductor chip having a front surface and a back surface opposite the front surface, and the semiconductor chip having side surfaces between the front surface and the back surface;

a contact pad on the front surface of the semiconductor chip;

a mold material layer on the back surface and side surfaces of the semiconductor chip, the mold material layer having a front surface and a back surface opposite the front surface, and the mold material layer having side surfaces between the front surface and the back surface, wherein the front surface of the mold material layer is co-planar with the front surface of the semiconductor chip;

a material layer on the front surface of the mold material and on the front surface of the semiconductor chip, the material layer having side surfaces in vertical alignment with the side surfaces of the mold material layer;

a solder resist layer on the material layer, the solder resist layer having side surfaces in vertical alignment with the side surfaces of the mold material layer;

an electrical conductor in the material layer, the electrical conductor in contact with the contact pad, and the electrical conductor having a width; and

a conductive contact area in the solder resist layer, the conductive contact area in contact with the electrical conductor, the electrical contact area having a width greater than a width of the electrical conductor, and the conductive contact area having a surface non-co-planar with the solder resist layer.

15. The semiconductor chip package of claim 14 , wherein the material layer comprises a preimpregnated foil.

16. The semiconductor chip package of claim 14 , wherein the mold material layer comprises an aliphatic polymer.

17. The semiconductor chip package of claim 14 , wherein the mold material layer comprises an aromatic polymer.

18. The semiconductor chip package of claim 14 , wherein the mold material layer comprises a thermoplastic polymer.

19. The semiconductor chip package of claim 14 , wherein the mold material layer comprises a thermoset polymer.

20. The semiconductor chip package of claim 14 , further comprising:

a solder ball on the conductive contact area, the solder ball in an opening in the solder resist layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061827/0686 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →