CMOS device with metal and silicide gate electrodes and a method for making it
View Patent ↗A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
1. A method for making a semiconductor device comprising:
forming a first polysilicon layer, which is bracketed by a pair of sidewall spacers, on a first gate dielectric layer, and a p-type polysilicon layer on a second gate dielectric layer;
removing the first polysilicon layer to generate a trench that is positioned between the pair of sidewall spacers, wherein a wet etch process having a source of hydroxide that is selective for an exposed region of the first polysilicon layer over an exposed region of the p-type polysilicon layer is applied to remove the first polysilicon layer without removing significant portions of the p-type polysilicon layer;
forming a n-type metal layer within the trench; and
converting substantially all of the p-type polysilicon layer to a silicide.
2. The method of claim 1 wherein the first gate dielectric layer and the second gate dielectric layer each comprise silicon dioxide, and wherein the first polysilicon layer and the p-type polysilicon layer are each between about 100 and about 2,000 angstroms thick.
3. The method of claim 1 wherein the n-type metal layer comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, and a metal carbide, and wherein all of the p-type polysilicon layer is converted to a silicide.
4. The method of claim 1 , wherein the trench has sidewalls defined by pair of sidewall spacers, and the sidewalls of the trench do not include the first gate dielectric material.
5. The method of claim 1 , wherein the first dielectric layer does not extend to the top of the trench.
6. The method of claim 1 , wherein the p-type polysilicon layer is bracketed by a second pair of sidewall spacers and the silicide substantially fills a volume between the second pair of sidewall spacers, above the second gate dielectric layer, and below a top of the second pair of sidewall spacers.
7. A method for making a semiconductor device comprising:
forming a first polysilicon layer, which is bracketed by a first pair of sidewall spacers, on a first gate dielectric layer;
forming a p-type polysilicon layer bracketed by a second pair of sidewall spacers;
removing the first polysilicon layer to generate a trench that is positioned between the first pair of sidewall spacers, wherein a wet etch process having a source of hydroxide that is selective for an exposed region of the first polysilicon layer over an exposed region of the p-type polysilicon layer is applied to remove the first polysilicon layer without removing significant portions of the p-type polysilicon layer;
forming a NMOS transistor on a substrate, the NMOS transistor having the first gate dielectric layer consisting of a first material, the first pair of sidewall spacers with a height, and a first gate electrode on the first gate dielectric layer and bracketed by the first pair of sidewall spacers, the first gate electrode comprising a metal; and
forming a PMOS transistor on the substrate, the PMOS transistor having a second gate dielectric layer consisting of a second material different than the first material, the second pair of sidewall spacers with a height, and a second gate electrode on the second gate dielectric layer and bracketed by the second pair of sidewall spacers, the second gate electrode comprising a p-type silicide.
8. The method of claim 7 , wherein the first gate dielectric layer comprises a high-k material and the second gate dielectric layer comprises a silicon oxide.
9. The method of claim 7 , wherein forming the NMOS and PMOS transistors comprises:
forming the first gate electrode within the trench; and
converting substantially all of the p-type polysilicon layer to the p-type silicide.
10. The method of claim 9 , wherein the first dielectric layer does not extend to the top of the trench.
11. The method of claim 9 , wherein the silicide substantially fills a volume between the second pair of sidewall spacers, above the second gate dielectric layer, and below a top of the second pair of sidewall spacers.