Integrated circuit incorporating higher voltage devices and low voltage devices therein
View Patent ↗An integrated circuit formed on a semiconductor substrate and configured to accommodate higher voltage devices and low voltage devices therein. In one embodiment, the integrated circuit includes a switch formed on the semiconductor substrate and a driver switch of a driver configured to provide a drive signal to the switch and embodied in a transistor. The transistor includes a gate located over a channel region recessed into a semiconductor substrate, and a source/drain including a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The transistor also includes an oppositely doped well located under and within the channel region. The transistor still further includes a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.
1. An integrated circuit formed on a semiconductor substrate, comprising:
a switch formed on said semiconductor substrate; and
a driver switch of a driver configured to provide a drive signal to said switch and embodied in a transistor, including:
a gate located over a channel region recessed into a semiconductor substrate,
a source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent said lightly doped region,
an oppositely doped well with respect to said lightly and heavily doped regions located under and within said channel region, and
a doped region of like type to said heavily doped region and adjoining said heavily doped region and said oppositely doped well, said doped region having a doping concentration profile less than a doping concentration profile of said heavily doped region.
2. The integrated circuit as recited in claim 1 wherein said switch is a transistor, including:
a gate located over a channel region recessed into said semiconductor substrate,
a source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent said lightly doped region, and
an oppositely doped well with respect to said lightly and heavily doped regions of said switch located under and within said channel region.
3. The integrated circuit as recited in claim 2 wherein said transistor employable as said switch further includes a doped region, located between said heavily doped region and said oppositely doped well, having a doping concentration profile less than a doping concentration profile of said heavily doped region.
4. The integrated circuit as recited in claim 1 wherein said transistor, further includes:
another source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent said lightly doped region; and
another doped region, located between said heavily doped region of said another source/drain and said oppositely doped well, having a doping concentration profile less than a doping concentration profile of said heavily doped region of said another source/drain.
5. The integrated circuit as recited in claim 1 wherein said transistor further includes a gate dielectric layer underlying said gate and gate sidewall spacers about said gate.
6. The integrated circuit as recited in claim 1 wherein said transistor further includes metal contacts formed over a salicide layer on said gate and said source/drain.
7. The integrated circuit as recited in claim 1 wherein said transistor is a laterally diffused metal oxide semiconductor device.
8. The integrated circuit as recited in claim 1 wherein an oppositely doped buried layer is located under said doped region.
9. The integrated circuit as recited in claim 1 further comprising a shallow trench isolation region located adjacent said heavily doped region opposite said lightly doped region within said semiconductor substrate.
10. The integrated circuit as recited in claim 1 further comprising a complementary metal oxide semiconductor device, formed on said semiconductor substrate, that includes a source/drain having a heavily doped region with a doping concentration profile different from said doping concentration profile of said heavily doped region of said source/drain of said transistor.
11. An integrated circuit formed on a semiconductor substrate, comprising:
a switch formed on a semiconductor substrate;
a driver switch of a driver configured to provide a drive signal to said switch and embodied in a laterally diffused metal oxide semiconductor device, including:
a gate located over a channel region recessed into a semiconductor substrate,
a source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent said lightly doped region,
an oppositely doped well with respect to said lightly and heavily doped regions located under and within said channel region, and
a doped region of like type to said heavily doped region and adjoining said heavily doped region and said oppositely doped well, said doped region having a doping concentration profile less than a doping concentration profile of said heavily doped region; and
a complementary metal oxide semiconductor device formed on said semiconductor substrate.
12. The integrated circuit as recited in claim 11 wherein said switch is referenced to a voltage level different from said driver switch and said switch is a transistor, including:
a gate located over a channel region recessed into said semiconductor substrate,
a source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent said lightly doped region, and
an oppositely doped well with respect to said lightly and heavily doped regions of said switch located under and within said channel region.
13. The integrated circuit as recited in claim 12 wherein said transistor employable as said switch further includes a doped region, located between said heavily doped region and said oppositely doped well, having a doping concentration profile less than a doping concentration profile of said heavily doped region.
14. The integrated circuit as recited in claim 11 wherein said laterally diffused metal oxide semiconductor device, further includes:
another source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent said lightly doped region; and
another doped region, located between said heavily doped region of said another source/drain and said oppositely doped well, having a doping concentration profile less than a doping concentration profile of said heavily doped region of said another source/drain.
15. The integrated circuit as recited in claim 11 wherein said laterally diffused metal oxide semiconductor device further includes a gate dielectric layer underlying said gate and gate sidewall spacers about said gate.
16. The integrated circuit as recited in claim 11 wherein said laterally diffused metal oxide semiconductor device further includes metal contacts formed over a salicide layer on said gate and said source/drain.
17. The integrated circuit as recited in claim 11 wherein said laterally diffused metal oxide semiconductor device is a P-type laterally diffused metal oxide semiconductor device.
18. The integrated circuit as recited in claim 11 wherein an oppositely doped buried layer is located under said doped region.
19. The integrated circuit as recited in claim 11 further comprising a shallow trench isolation region located adjacent said heavily doped region opposite said lightly doped region within said semiconductor substrate.
20. The integrated circuit as recited in claim 11 wherein said complementary metal oxide semiconductor device includes a source/drain having a heavily doped region with a doping concentration profile different from said doping concentration profile of said heavily doped region of said source/drain of said transistor.
21. The integrated circuit as recited in claim 1 wherein said heavily doped region is adjacent to but not surrounded by said lightly doped region.
22. The integrated circuit as recited in claim 11 wherein said heavily doped region is adjacent to but not surrounded by said lightly doped region.