System and process for fabricating semiconductor packages
View Patent ↗A method of processing semiconductor chips includes measuring locations of semiconductor dies placed on a carrier with a scanner to generate die location information. The method includes applying a dielectric layer over the semiconductor dies and communicating the die location information to a laser assembly. The method includes aligning the laser assembly with the carrier and laser structuring the dielectric layer with the laser assembly based on the die location information generated by the scanner.
1. A system configured to expedite of processing semiconductor chips, the system comprising:
a scanner configured to generate die location information for singulated semiconductor dies placed on a carrier and calculate exposure location information for each semiconductor die, wherein the semiconductor dies are encapsulated to form a reconfigured wafer on the carrier; and
a photolithographic stepper configured to receive the exposure location information from the scanner;
wherein the photolithographic stepper is aligned with the carrier only once prior to exposing the semiconductor dies.
2. The system of claim 1 , wherein the semiconductor chips comprise a contact pad, and the exposure location information is employed by the photolithographic stepper to open a dielectric layer to form a through-hole communicating with the contact pad.
3. The system of claim 2 , wherein the exposure location information is employed by the photolithographic stepper to open a resist layer disposed over the dielectric layer and pattern a redistribution layer into the resist layer.
4. The system of claim 3 , wherein the exposure location information is employed by the photolithographic stepper to open a solder resist layer disposed over the redistribution layer to expose a selected portion of the redistribution layer.
5. The system of claim 4 , further comprising: a solder ball connected to the selected portion of the redistribution layer.