Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same
View Patent ↗An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.
1. A transistor having a gate located over a channel region recessed into a semiconductor substrate, comprising:
a source/drain including a heavily doped region adjacent said channel region;
another source/drain having a lightly doped region adjacent an opposing side of said channel region;
an oppositely doped well under said channel region said heavily doped region of said source/drain and said lightly doped region of said another source/drain;
and a channel extension, within said oppositely doped well, under at least a portion of said channel region and extending under at least a portion of said heavily doped region of said source/drain and said lightly doped region of said another source/drain, wherein said channel extension extends under said portion of said lightly doped region of said another source/drain by a channel extension length.
2. The transistor as recited in claim 1 wherein said channel extension extends under said portion of said heavily doped region of said source/drain by a channel extension length.
3. The transistor as recited in claim 1 wherein said channel extension is of like type to said oppositely doped well.
4. The transistor as recited in claim 1 wherein said channel extension has a doping concentration profile greater than a doping concentration profile of said oppositely doped well.
5. The transistor as recited in claim 1 further comprising an isolation region adjacent said heavily doped region of said source/drain.
6. The transistor as recited in claim 1 wherein said channel extension has a doping concentration greater than a doping concentration profile of said channel region.
7. The transistor as recited in claim 1 wherein said another source/drain includes a heavily doped region adjacent said lightly doped region.
8. The transistor as recited in claim 1 wherein said another source/drain includes a heavily doped region adjacent said lightly doped region, said channel extension extending under a portion of said heavily doped region of said another source/drain.
9. The transistor as recited in claim 1 wherein said another source/drain includes a heavily doped region adjacent but not surrounded by said lightly doped region of said another source/drain.
10. The transistor as recited in claim 1 wherein said another source/drain includes a heavily doped region adjacent but not surrounded by said lightly doped region of said another source/drain, said channel extension extending under said portion of said lightly doped region of said another source/drain by a channel extension length.
11. The transistor as recited in claim 1 , further comprising
a doped region adjacent said oppositely doped well and extending under a portion of said lightly doped region of said another source/drain.
12. The transistor as recited in claim 1 , further comprising
a doped region adjacent said oppositely doped well and extending under a portion of said lightly doped region of said another source/drain; and
an oppositely doped buried layer under said doped region.
13. The transistor as recited in claim 1 further comprising a gate dielectric layer underlying said gate and gate sidewall spacers formed about said gate.
14. The transistor as recited in claim 1 further comprising metal contacts formed over a salicide layer formed on said gate and said source/drain.
15. The transistor as recited in claim 1 wherein said oppositely doped well has a retrograde doping concentration profile with about 1·10 17 atoms/centimeter 3 in a middle area thereof.
16. The transistor as recited in claim 1 wherein said oppositely doped well has a retrograde doping concentration profile with higher doping concentration profile at a top surface and a bottom surface compared to a middle area thereof.
17. The transistor as recited in claim 1 wherein said channel extension has a doping concentration profile of about 1.2·10 18 atoms/centimeter 3 .
18. The transistor as recited in claim 1 wherein said gate has a thickness in a range from about 100 to 500 nanometers.
19. The transistor as recited in claim 1 wherein heavily doped region of said source/drain is P-type, and said oppositely doped well and said channel extension are N-type.