IP Library Granted Patent US 7,477,641
Granted Patent B2
US 7,477,641 · App. 11/026,652 · Granted Jan 13, 2009

Providing access to data shared by packet processing threads

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,477,641
App. No.
11/026,652
Granted
Jan 13, 2009
Kind
B2
Abstract

In general, in one aspect, the disclosure describes a method that includes at a first packet processing thread executing at a first core, performing a memory read to data shared between packet processing threads including the first thread. The method also includes at the first packet processing thread, determining whether the data returned by the memory read has been changed by a packet processing thread operating on another core before performing an exclusive operation on the shared data by the first packet processing thread.

Claims (21)

1. A system comprising:

multiple multi-thread programmable cores integrated on a single die;

logic to:

process packets using a sequence of packet processing threads provided by the multiple multi-threaded programmable cores, the sequence of threads spanning a sequence of cores including, at least, a first core, a second core, and a third core, individual threads including at least one critical section that coordinates access to data shared by the threads;

wherein a thread in the sequence of packet processing threads executing on the first core performs operations comprising:

issuing a first signal to the third core permitting a pre-critical section read of shared data protected by a first critical section;

wherein a thread in the sequence of packet processing threads executing on the second core performs operations comprising:

executing the first critical section; and

if the data shared is modified within the first critical section, sending one or more messages to the third core identifying changes; and

wherein a thread in the sequence of packet processing threads executing on the third core performs operations comprising:

receiving the first signal from the first core;

after receiving the first signal from the first core, performing a memory access to retrieve a copy of data shared by the packet processing threads before entering the critical section that coordinates access to the shared data;

determining whether the data shared by the packet processing threads has changed from the copy based on whether the third core received the at least one or more messages identifying the changes to the data shared;

if the data has not changed, using the retrieved data in the critical section;

if the data has changed, using the changed data in the critical section.

2. The system of claim 1 ,

wherein the one or more messages are transmitted from the second core to the third core via a direct connection between the second core and the third core.

3. The system of claim 1 ,

wherein the determining whether the data shared by the packet has changed comprises performing a lookup based on an identifier associated with a packet.

4. The system of claim 3 , wherein the lookup comprises Content Addressable Memory (CAM) search.

5. The system of claim 4 , wherein the CAM is logically segmented into sets of entries associated with different critical sections executed by the threads.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061827/0686 →