Method for fabricating a semiconductor and semiconductor package
View Patent ↗A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
1. A semiconductor chip package, comprising:
a semiconductor chip having a front surface and a back surface opposite the front surface, and the semiconductor chip having side surfaces between the front surface and the back surface;
a contact pad on the front surface of the semiconductor chip;
a mold material layer on the back surface and side surfaces of the semiconductor chip, the mold material layer having a front surface and a back surface opposite the front surface, and the mold material layer having side surfaces between the front surface and the back surface, wherein the front surface of the mold material layer is co-planar with the front surface of the semiconductor chip;
a material layer on the front surface of the mold material and on the front surface of the semiconductor chip, the material layer having side surfaces in vertical alignment with the side surfaces of the mold material layer;
an electrical conductor in the material layer and protruding from the material layer, the electrical conductor in contact with the contact pad; and
a conductive contact area on the material layer, the conductive contact area in contact with sides of a portion of the electrical conductor protruding from the material layer.
2. The semiconductor chip package of claim 1 , wherein the material layer comprises a preimpregnated foil.
3. The semiconductor chip package of claim 1 , wherein the mold material layer comprises an aliphatic polymer.
4. The semiconductor chip package of claim 1 , wherein the mold material layer comprises an aromatic polymer.
5. The semiconductor chip package of claim 1 , wherein the mold material layer comprises a thermoplastic polymer.
6. The semiconductor chip package of claim 1 , wherein the mold material layer comprises a thermoset polymer.
7. The semiconductor chip package of claim 1 , further comprising:
a solder ball on the conductive contact area.
8. The semiconductor chip package of claim 1 , wherein the conductive contact area has a surface co-planar with the electrical conductor.
9. A semiconductor chip package, comprising:
a semiconductor chip having a front surface and a back surface opposite the front surface, and the semiconductor chip having side surfaces between the front surface and the back surface;
a contact pad on the front surface of the semiconductor chip;
a mold material layer on the side surfaces of the semiconductor chip, the mold material layer having a front surface and a back surface opposite the front surface, and the mold material layer having side surfaces between the front surface and the back surface, wherein the front surface of the mold material layer is co-planar with the front surface of the semiconductor chip;
a material layer on the front surface of the mold material and on the front surface of the semiconductor chip, the material layer having side surfaces in vertical alignment with the side surfaces of the mold material layer;
an electrical conductor in the material layer and protruding from the material layer, the electrical conductor in contact with the contact pad; and
a conductive contact area on the material layer, the conductive contact area in contact with sides of a portion of the electrical conductor protruding from the material layer.
10. The semiconductor chip package of claim 9 , wherein the material layer comprises a preimpregnated foil.
11. The semiconductor chip package of claim 9 , wherein the mold material layer comprises an aliphatic polymer.
12. The semiconductor chip package of claim 9 , wherein the mold material layer comprises an aromatic polymer.
13. The semiconductor chip package of claim 9 , wherein the mold material layer comprises a thermoplastic polymer.
14. The semiconductor chip package of claim 9 , wherein the mold material layer comprises a thermoset polymer.
15. The semiconductor chip package of claim 9 , further comprising:
a solder ball on the conductive contact area.
16. The semiconductor chip package of claim 9 , wherein the conductive contact area has a surface co-planar with the electrical conductor.