Method for fabricating a semiconductor and semiconductor package
View Patent ↗A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
1. A method for fabricating a semiconductor chip module, comprising:
providing a first layer and a layer stack disposed on the first layer, the layer stack comprising a seed layer and a second layer;
applying a plurality of semiconductor chips above the second layer; and
separating the layer stack with the applied semiconductor chips from the first layer.
2. The method of claim 1 , further comprising:
applying the first layer and the layer stack onto a base layer;
applying the plurality of semiconductor chips above the second layer; and
separating the layer stack with the applied semiconductor chips from the first layer.
3. The method of claim 1 , further comprising:
covering the semiconductor chips and the second layer with a material layer.
4. The method of claim 3 , further comprising:
the covering comprises molding.
5. The method of claim 1 , comprising wherein the second layer is a dielectric layer.
6. The method of claim 1 , further comprising:
forming a plurality of electrical conductors extending through the layer stack to connect to contact pads on surfaces of the semiconductor chips, respectively.
7. The method of claim 6 , further comprising:
fabricating a wiring layer onto the second layer, the wiring layer comprising electrically conductive contact areas connected to the electrical conductors.
8. The method of claim 7 , further comprising:
fabricating the contact areas by a plating process, in particular by a chemical plating process.
9. A method for fabricating a semiconductor chip module, comprising:
providing a first layer and a layer stack disposed on the first layer, the layer stack comprising a second layer and a photoresist layer;
applying a plurality of semiconductor chips above the second layer; and
separating the layer stack with the applied semiconductor chips from the first layer.
10. The method of claim 9 , comprising:
developing the photoresist layer to define openings to contacts on the semiconductor chips.
11. The method of claim 10 , comprising:
forming the openings in the second layer.
12. The method of claim 11 , comprising:
forming openings in the second layer using an ablation process.
13. The method of claim 11 , comprising:
forming openings in the second layer using an etching process.
14. The method of claim 9 , comprising:
forming openings through the layer stack, to define vias, to contacts located on the semiconductor chips.
15. The method of claim 14 , comprising:
filling the vias with an at least partially conductive material.
16. The method of claim 15 , comprising:
metalizing the filled vias to produce contact areas.
17. The method of claim 14 , comprising:
filling the vias with a solder material.
18. The method of claim 14 , comprising:
filling the vias with an electrically conductive ink.
19. The method of claim 9 , comprising:
the layer stack further comprising a seed layer.