Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same
View Patent ↗An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.
1. An integrated circuit employable with a power converter, comprising:
a power switch of a power train of said power converter formed on a semiconductor substrate; and
a driver switch of a driver configured to provide a drive signal to said power switch and embodied in a transistor, including:
a gate located over a channel region recessed into said semiconductor substrate,
a source/drain including a lightly doped region adjacent said channel region,
an oppositely doped well extending under said channel region and a portion of said lightly doped region of said source/drain, and
a channel extension, within said oppositely doped well, under said channel region and extending under a portion of said lightly doped region of said source/drain.
2. The integrated circuit as recited in claim 1 wherein said channel extension extends under said portion of said lightly doped region of said source/drain by a channel extension length.
3. The integrated circuit as recited in claim 1 wherein said channel extension is of like type to and has a doping concentration profile greater than a doping concentration profile of said oppositely doped well.
4. The integrated circuit as recited in claim 1 wherein said source/drain includes a heavily doped region adjacent said lightly doped region of said source/drain.
5. The integrated circuit as recited in claim 1 wherein said source/drain includes a heavily doped region adjacent but not surrounded by said lightly doped region of said source/drain.
6. The integrated circuit as recited in claim 1 wherein said source/drain includes a heavily doped region adjacent said lightly doped region, said driver switch further comprising an isolation region adjacent said heavily doped region of said source/drain.
7. The integrated circuit as recited in claim 1 wherein said driver switch further comprises another source/drain having a lightly doped region adjacent an opposing side of said channel region, said channel extension extending under a portion of said lightly doped region of said another source/drain by a channel extension length.
8. The integrated circuit as recited in claim 1 wherein said driver switch further comprises another source/drain having a heavily doped region adjacent an opposing side of said channel region, said channel extension extending under a portion of said heavily doped region of said another source/drain by a channel extension length.
9. The integrated circuit as recited in claim 1 wherein said driver switch, further comprises:
a doped region adjacent said oppositely doped well and extending under a portion of said lightly doped region of said source/drain; and
an oppositely doped buried layer under said doped region.
10. The integrated circuit as recited in claim 1 wherein said driver switch further comprises a gate dielectric layer underlying said gate and gate sidewall spacers formed about said gate, said driver switch further comprising metal contacts formed over a salicide layer formed on said gate and said source/drain.
11. The integrated circuit as recited in claim 1 wherein said driver switch further comprises a gate dielectric layer underlying said gate and gate sidewall spacers formed about said gate, said driver switch further comprising metal contacts formed over a salicide layer formed on said gate and said source/drain.
12. An integrated circuit employable with a power converter, comprising:
a power switch of a power train of said power converter formed on a semiconductor substrate; and
a driver switch of a driver configured to provide a drive signal to said power switch and embodied in a transistor, including:
a gate located over a channel region recessed into said semiconductor substrate,
a source/drain including a heavily doped region adjacent said channel region,
an oppositely doped well extending under said channel region and a portion of said heavily doped region of said source/drain, and
a channel extension, within said oppositely doped well, under said channel region and extending under a portion of said heavily doped region of said source/drain.
13. The integrated circuit as recited in claim 12 wherein said channel extension extends under said portion of said heavily doped region of said source/drain by a channel extension length.
14. The integrated circuit as recited in claim 12 wherein said channel extension is of like type to said oppositely doped well.
15. The integrated circuit as recited in claim 12 wherein said channel extension has a doping concentration profile greater than a doping concentration profile of said oppositely doped well.
16. The integrated circuit as recited in claim 12 wherein said driver switch further comprises an isolation region adjacent said heavily doped region of said source/drain.
17. The integrated circuit as recited in claim 12 wherein said driver switch further comprises another source/drain having a lightly doped region adjacent an opposing side of said channel region, said channel extension extending under a portion of said lightly doped region of said another source/drain by a channel extension length.
18. The integrated circuit as recited in claim 12 wherein said driver switch further comprises another source/drain having a lightly doped region and a heavily doped region adjacent an opposing side of said channel region, said channel extension extending under a portion of said lightly doped region of said another source/drain by a channel extension length.
19. The integrated circuit as recited in claim 12 wherein said driver switch further comprises another source/drain having a lightly doped region adjacent an opposing side of said channel region and a heavily doped region adjacent but not surrounded by said lightly doped region of said another source/drain, said channel extension extending under a portion of said lightly doped region of said another source/drain by a channel extension length.
20. The integrated circuit as recited in claim 12 wherein said driver switch, further comprises:
another source/drain having a lightly doped region adjacent an opposing side of said channel region;
a doped region adjacent said oppositely doped well and extending under a portion of said lightly doped region of said another source/drain; and
an oppositely doped buried layer under said doped region.