Workpiece with semiconductor chips, semiconductor device and method for producing a workpiece with semiconductor chips
View Patent ↗A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
1. A workpiece, comprising:
a plurality of semiconductor chips arranged in rows and columns as a grid of semiconductor chips, each of the plurality of semiconductor chips having a first main surface and a second main surface;
an electrically conducting layer arranged on at least one region of the second main surface, wherein the electrically conducting layer electrically couples the plurality of semiconductor chips with one another via contact strip regions in interspaces between the semiconductor chips, the contact strip regions forming a grid structure; and
a molding compound arranged on the electrically conductive layer and residing at a position coplanar with the first main surface of the semiconductor chips in areas between the semiconductor chips not containing the contact strip regions of the electrically conducting layer.
2. The workpiece of claim 1 , wherein the electrically conducting layer is arranged on at least one region of at least one side surface of the plurality of semiconductor chips.
3. The workpiece of claim 2 , wherein the at least one side surface of the plurality of semiconductor chips are embedded in the molding compound.
4. The workpiece of claim 1 , wherein at least one region of the electrically conducting layer is arranged on a first main surface of the workpiece.
5. The workpiece of claim 1 , wherein at least one region of the electrically conducting layer is exposed from the molding compound.
6. The workpiece of claim 1 , wherein an electrically insulating material is arranged between each semiconductor chip and the electrically conducting layer.
7. The workpiece of claim 6 , wherein the electrically conducting layer forms an electromagnetic shielding for the plurality of semiconductor chips.
8. The workpiece of claim 1 , wherein the first main surface of the plurality of semiconductor chips comprises an active structure.
9. The workpiece of claim 1 , wherein the second main surface of the plurality of semiconductor chips is a rear side of the semiconductor chip.
10. The workpiece of claim 1 , wherein the electrically conducting layer is embedded in the molding compound.
11. The workpiece of claim 1 , wherein the first main surface of the workpiece comprises a wiring layer.