Offset compensated sensing for magnetic random access memory
View Patent ↗An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the output of the differential amplifier. The compensation circuit of the differential amplifier includes a compensation capacitor that stores a compensation voltage during a calibration phase, and applies the stored compensation voltage to a compensation input of the compensation circuit of the amplifier during a measurement phase. Feedback from a source of the transistor controls the output of the differential amplifier to maintain a standard voltage across a resistive memory element connected to the source during measurement of the resistance of the resistive memory element, and the compensation circuit improves the accuracy of the voltage across the resistive memory element by compensating for an offset voltage of the differential amplifier.
1. A memory element voltage supply comprising:
a transistor including a gate and a transistor terminal, said gate adapted to control an electrical current passing through said transistor in relation to a voltage applied at said gate, said transistor terminal operatively connected to an impedance memory element;
a differential amplifier circuit including a first input operatively connected to a source of a reference voltage, a second input switchingly connected to said transistor terminal, and a first output switchingly connected to said gate; and
a compensation amplifier circuit including a third input adapted to receive and store a first compensation voltage, and a second output operatively connected to said first output.
2. A voltage supply as defined in claim 1 wherein said transistor is an N-channel transistor.
3. A voltage supply as defined in claim 1 wherein said transistor is an P-channel transistor.
4. A voltage supply as defined in claim 1 , further comprising a fourth input and a capacitor connected between said fourth input and a source of constant potential voltage.
5. A voltage supply as defined in claim 4 , wherein said source of constant potential voltage is at a ground potential.
6. A voltage supply as defined in claim 4 , wherein said first input is switchingly connected to said third input such that during a first calibration time period said first input is operatively connected to said third input and during a second measurement time period said first input is isolated from said third input.
7. A voltage supply as defined in claim 6 , wherein said third input comprises a non-inverting input, further comprising a capacitor connected between said non-inverting input and ground.
8. A voltage supply as defined in claim 1 , wherein said differential amplifier operates between supply voltage and ground, and wherein said source of a reference voltage supplies a reference voltage intermediate to said supply voltage and ground.
9. A voltage supply as defined in claim 6 , wherein said impedance memory device comprises a resistive memory device adapted to represent a logical value as a device resistance.
10. A magnetic random access memory device comprising:
a resistive memory element and a voltage supply including a transistor having a gate, said gate adapted to control an electrical current through said transistor in relation to a voltage applied at said gate, said transistor further having a transistor source operatively connected to said resistive memory device;
a differential amplifier portion including a first input operatively connected to a source of a reference voltage, a second input, a first output switchingly connected to said gate, and a second complementary output;
a compensation amplifier portion including a third input adapted to receive a first compensation voltage, a fourth input adapted to receive and store a second compensation voltage, a third output operatively connected to said first output, and a fourth complementary output operatively connected to said second output; and
a feedback line adapted to switchingly connect said second input to said transistor source.