Selective power-down for high performance CPU/system

1. A computer program product comprising a computer useable medium having computer program logic recorded thereon for enabling a microprocessor to compile a source code program, said computer program logic comprising:

means for enabling the microprocessor to receive a plurality of source code instructions;

means for enabling the microprocessor to convert each of said source code instructions into one or more machine code instructions;

means for enabling the microprocessor to generate monitoring information corresponding to each of said machine code instructions, said monitoring information for indicating which of a plurality of functional units of a microelectronic device are to be selectively activated for executing each of said machine code instructions; and

means for enabling the microprocessor to output said machine code instructions and said corresponding monitoring information.

2. The computer program product of claim 1 , wherein said means for enabling the microprocessor to generate monitoring information comprises means for enabling the microprocessor to generate information indicating that a floating point unit of said microelectronic device is to be selectively activated for executing a machine code instruction.

3. The computer program product of claim 1 , wherein said means for enabling the microprocessor to generate monitoring information comprises means for enabling the microprocessor to generate information indicating that a cache control unit of said microelectronic device is to be selectively activated for executing a machine code instruction.

4. The computer program product of claim 1 , wherein said means for enabling the microprocessor to generate monitoring information comprises means for enabling the microprocessor to generate information indicating that an integer unit of said microelectronic device is to be selectively activated for executing a machine code instruction.

5. The computer program product of claim 1 , wherein said means for enabling the microprocessor to generate monitoring information comprises means for enabling the microprocessor to generate information indicating that a memory control unit of said microelectronic device is to be selectively activated for executing a machine code instruction.

6. The computer program product of claim 1 , wherein said means for enabling the microprocessor to generate monitoring information comprises means for enabling the microprocessor to generate information indicating that a graphics unit of said microelectronic device is to be selectively activated for executing a machine code instruction.

7. The computer program product of claim 1 , wherein said means for enabling the microprocessor to generate monitoring information comprises means for enabling the processor to generate a data block that is appended to each of said machine code instructions.

8. The computer program product of claim 1 , further comprising:

means for enabling the microprocessor to reorder said machine code instructions to optimize a reduction in power consumption by said microelectronic device when said microelectronic device executes said machine code instructions.

9. A computer program product comprising a computer useable medium having computer program logic recorded thereon for enabling a microprocessor to compile a source code program, said computer program logic comprising:

means for enabling the microprocessor to receive a plurality of source code instructions;

means for enabling the microprocessor to convert each of said source code instructions into one or more machine code instructions;

means for enabling the microprocessor to generate monitoring information corresponding to each of said machine code instructions, said monitoring information for indicating which of a plurality of functional units of the microprocessor are to be selectively activated for executing each of said machine code instructions; and

means for enabling the microprocessor to output said machine code instructions and said corresponding monitoring information.

10. The computer program product of claim 9 , wherein said means for enabling the microprocessor to generate monitoring information comprises means for enabling the microprocessor to generate information indicating that a floating point unit of the microprocessor is to be selectively activated for executing a machine code instruction.

11. The computer program product of claim 9 , wherein said means for enabling the microprocessor to generate monitoring information comprises means for enabling the microprocessor to generate information indicating that a cache control unit of the microprocessor is to be selectively activated for executing a machine code instruction.

12. The computer program product of claim 9 , wherein said means for enabling the microprocessor to generate monitoring information comprises means for enabling the microprocessor to generate information indicating that an integer unit of the microprocessor is to be selectively activated for executing a machine code instruction.

13. The computer program product of claim 9 , wherein said means for enabling the microprocessor to generate monitoring information comprises means for enabling the microprocessor to generate information indicating that a memory control unit of the microprocessor is to be selectively activated for executing a machine code instruction.

14. The computer program product of claim 9 , wherein said means for enabling the microprocessor to generate monitoring information comprises means for enabling the microprocessor to generate information indicating that a graphics unit of the microprocessor is to be selectively activated for executing a machine code instruction.

15. The computer program product of claim 9 , wherein said means for enabling the microprocessor to generate monitoring information comprises means for enabling the processor to generate a data block that is appended to each of said machine code instructions.

16. The computer program product of claim 9 , further comprising:

means for enabling the microprocessor to reorder said machine code instructions to optimize a reduction in power consumption by the microprocessor when the microprocessor executes said machine code instructions.

17. A computer program product comprising a computer useable medium having computer program logic recorded thereon for enabling a microprocessor to compile a source code program, said computer program logic comprising:

a receiving module enabling the microprocessor to receive a plurality of source code instructions;

a converting module enabling the microprocessor to convert each of said source code instructions into one or more machine code instructions;

a generating module enabling the microprocessor to generate monitoring information corresponding to each of said machine code instructions, said monitoring information for indicating which of a plurality of functional units of a microelectronic device are to be selectively activated for executing each of said machine code instructions; and

an output module enabling the microprocessor to output said machine code instructions and said corresponding monitoring information.

18. The computer program product of claim 17 , wherein said generating module comprises logic to generate information indicating that a floating point unit of said microelectronic device is to be selectively activated for executing a machine code instruction.

19. The computer program product of claim 17 , wherein said generating module comprises logic to generate information indicating that a cache control unit of said microelectronic device is to be selectively activated for executing a machine code instruction.

20. The computer program product of claim 17 , wherein said generating module comprises logic to generate information indicating that an integer unit of said microelectronic device is to be selectively activated for executing a machine code instruction.

21. The computer program product of claim 17 , wherein said generating module comprises logic to generate information indicating that a memory control unit of said microelectronic device is to be selectively activated for executing a machine code instruction.

22. The computer program product of claim 17 , wherein said generating module comprises logic to generate information indicating that a graphics unit of said microelectronic device is to be selectively activated for executing a machine code instruction.

23. The computer program product of claim 17 , wherein said generating module comprises logic to generate a data block that is appended to each of said machine code instructions.

24. The computer program product of claim 17 , further comprising:

a reordering module enabling the microprocessor to reorder said machine code instructions to optimize a reduction in power consumption by said microelectronic device when said microelectronic device executes said machine code instructions.

25. A computer program product comprising a computer useable medium having computer program logic recorded thereon for enabling a microprocessor to compile a source code program, said computer program logic comprising:

a receiving module enabling the microprocessor to receive a plurality of source code instructions;

a converting module enabling the microprocessor to convert each of said source code instructions into one or more machine code instructions;

a generating module enabling the microprocessor to generate monitoring information corresponding to each of said machine code instructions, said monitoring information for indicating which of a plurality of functional units of the microprocessor are to be selectively activated for executing each of said machine code instructions; and

an output module for enabling the microprocessor to output said machine code instructions and said corresponding monitoring information.

26. The computer program product of claim 25 , wherein said generating module comprises logic to generate information indicating that a floating point unit of the microprocessor is to be selectively activated for executing a machine code instruction.

27. The computer program product of claim 25 , wherein generating module comprises logic to generate information indicating that a cache control unit of the microprocessor is to be selectively activated for executing a machine code instruction.

28. The computer program product of claim 25 , wherein said generating module comprises logic to generate information indicating that an integer unit of the microprocessor is to be selectively activated for executing a machine code instruction.

29. The computer program product of claim 25 , wherein said generating module comprises logic to generate information indicating that a memory control unit of the microprocessor is to be selectively activated for executing a machine code instruction.

30. The computer program product of claim 25 , wherein said generating module comprises logic to generate information indicating that a graphics unit of the microprocessor is to be selectively activated for executing a machine code instruction.

31. The computer program product of claim 25 , wherein said generating module comprises logic to generate a data block that is appended to each of said machine code instructions.

32. The computer program product of claim 25 , further comprising:

a reordering module enabling the microprocessor to reorder said machine code instructions to optimize a reduction in power consumption by the microprocessor when the microprocessor executes said machine code instructions.