Patent Assignment
Reel/Frame 028153/0654
Assignment of Assignor's Interest
Recorded: 2012-05-03
Pages: 27
Assignor
SEIKO EPSON CORPORATION
Executed: 2011-12-06
Assignee
SAMSUNG ELECTRONICS CO., LTD.
416 MAETAN 3-DONG, YEONGTONG-GU, SUWON-SI, GYEONGGI-DO, 443-772, KOREA, REPUBLIC OF
Covered Properties
(139)
Microprocessor Architecture with a Switch Network for Data Transfer Between Cache, Memory Port, and Iou
Patent:
5,440,752 →
Application:
07/726,893 →
Semaphore Bypass
Patent:
5,261,106 →
Application:
07/805,838 →
Method for Generating Power Slits
Patent:
5,345,394 →
Application:
07/833,419 →
System and Method for Reducing the Critical Path in Memory Control Input/Output Control Unit Operations
Patent:
5,828,861 →
Application:
07/846,231 →
Register File Backup Queue
Patent:
5,398,330 →
Application:
07/846,237 →
Selective Power-Down for High Performance Cpu/System
Patent:
5,452,401 →
Application:
07/860,717 →
Semiconductor Floor Plan for a Register Renaming Circuit
Patent:
5,371,684 →
Application:
07/860,718 →
A System and Method for Transferring Data Between a Plurality of Virtual Fifos and a Peripheral via a Hardware Fifo and Selectively Updating Contro Information Associated with the Virtual Fifos
Patent:
5,444,853 →
Application:
07/862,623 →
Area-Efficient Multiplier for Use in an Integrated Circuit
Patent:
5,325,320 →
Application:
07/877,562 →
Low-Power Area-Efficient Absolute Value Arithmetic Unit
Patent:
5,251,164 →
Application:
07/887,511 →
System and Method for Reducing Ground Bounce in Integrated Circuit Output Buffers
Patent:
5,214,320 →
Application:
07/897,729 →
Polygon Rasterization
Patent:
5,446,836 →
Application:
07/968,901 →
System and Method for Synchronizing Processors in a Parallel Processing Environment
Patent:
5,440,746 →
Application:
07/972,699 →
System and Method for Supporting Context Switching Within a Multiprocessor System Having Functional Blocks That Generate State Programs with Coded Register Load Instructions
Patent:
5,428,779 →
Application:
07/973,344 →
Input Output Control Unit Having Dedicated Paths for Controlling the Input and Output of Data Between Host Processor and External Device
Patent:
5,499,384 →
Application:
07/997,943 →
System and Method for Assigning Tags to Instructions to Control Instruction Execution
Patent:
5,604,912 →
Application:
07/999,648 →
Area-Efficient Multiplier for Use in an Integrted Circuit
Patent:
5,257,217 →
Application:
08/046,716 →
Risc Microprocessor Architecture Implementing Fast Trap and Exception State
Patent:
5,448,705 →
Application:
08/065,063 →
Pixel Modification Unit for Use as a Functional Unit in a Superscalar Microprocessor
Patent:
5,533,185 →
Application:
08/141,966 →
System and Method for Assigning Tags to Control Instruction Processing in a Superscalar Processor
Patent:
5,628,021 →
Application:
08/224,328 →
Clock Generator with Programmable Non-Overlapping Clock Edge Capability
Patent:
5,444,405 →
Application:
08/255,910 →
Page Printer Controller Including a Single Chip Superscalar Microprocessor with Graphics Functional Units
Patent:
5,394,515 →
Application:
08/267,646 →
A Power Bus Having Power Slits Embodied Therein
Patent:
5,461,578 →
Application:
08/289,278 →
Z-Buffer Tag Memory Organization
Patent:
5,561,750 →
Application:
08/310,821 →
A System for Transferring Data Onto Buses Having Different Widths
Patent:
5,594,877 →
Application:
08/317,839 →
Integrated Circuit Device Implemented Using a Plurality of Partially Defective Integrated Circuit Chips
Patent:
5,581,562 →
Application:
08/325,946 →
Risc Microprocessor Architecture Implementing Fast Trap and Exception State
Patent:
5,481,685 →
Application:
08/345,333 →
An Apparatus and Method for Emulating a Microelectronic Device by Interconnecting and Running Test Vectors on Physically Implemented Functional Modules
Patent:
5,581,742 →
Application:
08/352,680 →
Integrated Structure Layout and Layout of Interconnections for an Integrated Circuit Chip
Patent:
5,566,385 →
Application:
08/353,299 →
High Density Buffer Architecture and Method
Patent:
5,630,091 →
Application:
08/357,166 →
Graphics Control Planes for Windowing and Other Display Operations
Patent:
5,515,494 →
Application:
08/366,423 →
Page Printer Controller Including a Single Chip Superscalar Microprocessor with Graphics Functional Units
Patent:
5,559,951 →
Application:
08/383,015 →
High-Performance, Superscalar-Based Computer System with Out-of-Order Instruction Execution and Concurrent Results Distribution
Patent:
5,560,032 →
Application:
08/397,016 →
Register File Backup Queue
Patent:
5,588,113 →
Application:
08/403,527 →
Hardware Architecture for Image Generation and Manipulation
Patent:
5,649,173 →
Application:
08/413,983 →
Multimprocessor System Having Dynamic Priority Based on Row Match of Previous Serviced Address, Number of Times Denied Service and Number of Times Serviced Without Interruption
Patent:
5,754,800 →
Application:
08/442,649 →
A Power Bus Having Power Slits and Holes Embodied Therein, and Method for Making the Same
Patent:
5,561,789 →
Application:
08/455,133 →
A Computer System Including a Page Printer Controller Including a Single Chip Supercalar Microprocessor with Graphical Functional Units
Patent:
5,564,117 →
Application:
08/468,083 →
High Density Buffer Memory Architecture
Patent:
5,600,815 →
Application:
08/469,928 →
Microprocessor Architecture with a Switch Network for Data Transfer Between Cache, Memory Port, and Iou
Patent:
5,604,865 →
Application:
08/474,385 →
System and Method for Register Renaming
Patent:
5,590,295 →
Application:
08/478,531 →
System and Method for Processing Multiple Requests and Out of Order Returns
Patent:
5,778,434 →
Application:
08/479,035 →
System and Method for Retiring Instructions in a Superscalar Microprocessor
Patent:
5,826,055 →
Application:
08/481,146 →
Selective Power-Down for High Performance Cpu/System
Patent:
5,655,124 →
Application:
08/487,976 →
A System for Transferring Data Using Value in Hardware Fifo's Unused Data Start Pointer to Update Virtual Fifo's Start Address Pointer for Fast Context Switching
Patent:
5,649,230 →
Application:
08/487,993 →
Power Bus Having Power Slits Embodied Therein and Method for Making the Same
Patent:
5,726,904 →
Application:
08/665,846 →
System and Method for Generating Supplemental Ready Signals to Eliminate Wasted Cycles Between Operations
Patent:
5,734,856 →
Application:
08/673,465 →
System and Method for Register Renaming
Patent:
5,809,276 →
Application:
08/698,211 →
High-Performance Superscalar-Based Computer System with Out-of-Order Instruction Execution and Concurrent Results Distribution
Patent:
5,832,292 →
Application:
08/716,728 →
Integrated Structure Layout and Layout of Interconnections for an Integrated Circuit Chip
Patent:
5,734,584 →
Application:
08/730,658 →
System for Supporting a Buffer Memory Wherein Data Is Stored in Multiple Data Widths Based Upon a Switch Interface for Detecting the Different Bus Sizes
Patent:
5,887,148 →
Application:
08/757,252 →
Register File Backup Queue
Patent:
5,881,216 →
Application:
08/771,911 →
Method for Manufacturing an Integrated Circuit with Programmable Non-Overlapping-Clock-Edge Capability
Patent:
5,966,037 →
Application:
08/795,363 →
System and Method for Assigning Tags to Instructions to Control Instruction Execution
Patent:
5,892,963 →
Application:
08/799,462 →
Space Saviing Method and Floor Plan for Fabricating an Integrated Circuit Comprising a High Density Buffer Memory
Patent:
5,806,084 →
Application:
08/800,507 →
System and Method for Assigning Tags to Control Instruction Processing in a Superscalar Processor
Patent:
5,896,542 →
Application:
08/811,237 →
Selective Power-Down for High Performance Cpu/System
Patent:
5,787,297 →
Application:
08/811,238 →
Hardware Architecture for Image Generation and Manipulation
Patent:
5,790,134 →
Application:
08/824,421 →
System and Method for Generating 3D Color Images with Simulated Light Sources
Patent:
5,896,135 →
Application:
08/903,496 →
Microprocessor Architecture with a Switch Network and an Arbitration Unit for Controlling Access to Memory Ports
Patent:
5,941,979 →
Application:
08/915,913 →
Integrated Structure Layout and Layout of Interconnections for an Instruction Execution Unit of an Integrated Circuit Chip
Patent:
5,831,871 →
Application:
08/980,057 →
Method for Manufacturing a Power Bus on a Chip
Patent:
5,909,377 →
Application:
08/997,605 →
System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor
Patent:
6,131,157 →
Application:
09/009,412 →
Computer System for Processing Multiple Requests and Out of Order Returns Using a Request Queue
Patent:
6,173,369 →
Application:
09/024,134 →
System and Method for Register Renaming
Patent:
6,138,231 →
Application:
09/063,059 →
Selective Power-Down for High Performance Cpu/System
Patent:
6,256,743 →
Application:
09/069,335 →
High-Performance Superscalar-Based Computer System with Out-of-Order Instruction Execution and Concurrent Results Distribution
Patent:
6,038,653 →
Application:
09/158,568 →
Integrated Structure Layout and Layout of Interconnections for an Integrated Circuit Chip
Patent:
6,083,274 →
Application:
09/173,560 →
Register File Backup Queue
Patent:
6,374,347 →
Application:
09/229,172 →
System and Method for Assigning Tags to Control Instruction Processing in a Superscalar Processor
Patent:
6,092,176 →
Application:
09/252,655 →
System and Method for Supporting a Multiple Width Memory Subsystem
Patent:
6,047,348 →
Application:
09/252,657 →
System and Method for Adjusting Priorities Associated with Multiple Devices Seeking Access to a Memory Array Unit
Patent:
6,219,763 →
Application:
09/253,760 →
Microprocessor Architecture Capable of Supporting Multiple Heterogeneous Processors
Patent:
6,272,579 →
Application:
09/253,761 →
Power Bus and Method for Generating Power Slits Therein
Patent:
6,233,721 →
Application:
09/270,738 →
Integrated Circuit with Hardware-Based Programmable Non-Overlapping-Clock-Edge Capability
Patent:
6,163,194 →
Application:
09/376,186 →
High Performance Superscalar-Based Computer System with Out-of-Order Instruction Execution and Concurrent Results Distribution
Patent:
6,282,630 →
Application:
09/393,662 →
System and Method for Register Renaming
Patent:
6,272,617 →
Application:
09/399,000 →
System and method for assigning tags to control instruction processing in a superscalar processor
Patent:
6,360,309 →
Application:
09/574,251 →
Integrated Structure Layout and Layout of Interconnections for an Instruction Execution Unit of an Integrated Circuit Chip
Patent:
6,401,232 →
Application:
09/604,419 →
System and Method for Retrining Approximately Simultaneously a Group of Nstructions in a Superscalar Microprocessor
Patent:
6,412,064 →
Application:
09/631,640 →
Method of Fabricating Semiconductor Device
Patent:
6,566,232 →
Application:
09/691,112 →
Clock Generator with Programmable Non-Overlapping-Clock-Edge- Capability
Power Bus and Method for Generating Power Slits Therein
System and Method for Register Renaming
High-Performance, Superscalar-Based Computer System with Out-of-Order Instruction Execution and Concurrent Results Distribution
Selective Power-Down for High Performance Cpu/System
Microprocessor Architecture Capable of Supporting Multiple Heterogeneous Processors
Semiconductor Device and Method of Manufacturing the Same, Circuit Board, and Electronic Equipment
Clock Generator with Programmable Non-Overlapping-Clock-Edge Capability
System and Method for Assigning Tags to Control Instruction Processing in a Superscalar Processor
Computer Program Product for Defining Slits in a Bus on a Chip
System and Method for Register Renaming
Register File Backup Queue
Semiconductor Device and Manufacturing Method Therefor, Circuit Substrate, and Electronic Apparatus
Integrated Structure Layout and Layout of Interconnections for an Instruction Execution Unit of an Integrated Circuit Chip
System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor
Selective Power-Down for High Performance Cpu/System
System and Method for Register Renaming
Register File Backup Queue
Clock Generator with Programmable Non-Overlapping-Clock-Edge Capability
Selective Power-Down for High Performance Cpu/System
Selective Power-Down for High Performance Cpu/System
Microprocessor Architecture Capable of Supporting Multiple Heterogeneous Processors
Clock Generator with Programmable Non-Overlapping-Clock-Edge Capability
Semiconductor Chip, and Semiconductor Wafer Including a Variable Thickness Insulating Layer
Method for Manufacturing Semiconductor Device, and Method for Manufacturing Semiconductor Module
Manufacturing Method for Semiconductor Device, Semiconductor Device, and Electronic Apparatus
Semiconductor Device, Method of Manufacturing Three-Dimensional Stacking Type Semiconductor Device, Circuit Board, and Electronic Instrument
Method of Manufacturing Semiconductor Device, Semiconductor Device, Circuit Substrate and Electronic Apparatus
System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor
Semiconductor Device, Stacked Semiconductor Device, Methods of Manufacturing Them, Circuit Board, and Electronic Instrument
System and Method for Assigning Tags to Control Instruction Processing in a Superscalar Processor
Integrated Structure Layout and Layout of Interconnections for an Instruction Execution Unit of an Integrated Circuit Chip
Method for Manufacturing a Power Bus on a Chip
Register File Backup Queue
Manufacturing Method of Semiconductor Device, Semiconductor Device, Circuit Substrate and Electronic Equipment
Clock Generator with Programmable Non-Overlapping-Clock-Edge Capability
System and Method for Handling Exceptions and Branch Mispredictions in a Superscalar Microprocessor
Method for Manufacturing Semiconductor Device and Semiconductor Device
Microprocessor Architecture Capable of Supporting Multiple Heterogeneous Processors
System and Method for Register Renaming
Semiconductor Device Manufacturing Method, Semiconductor Device, Laminated Semiconductor Device, Circuit Substrate, and Electronic Apparatus
Method of Manufacturing Semiconductor Device
High-Performance Superscalar-Based Computer System with Out-of-Order Instruction Execution and Concurrent Results Distribution
System and Method for Assigning Tags to Control Instruction Processing in a Superscalar Processor
Manufacturing Method for Semiconductor Device, Semiconductor Device, and Electronic Apparatus
Selective Power-Down for High Performance Cpu/System
Manufacturing Method for a Semiconductor Device
Method for Manufacturing a Power Bus on a Chip
High-Performance Superscalar-Based Computer System with Out-of Order Instruction Execution and Concurrent Results Distribution
System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor
Integrated Structure Layout and Layout of Interconnections for an Instruction Execution Unit of an Integrated Circuit Chip
Clock Generator with Programmable Non-Overlapping-Clock-Edge Capability
Register File Backup Queue
System and Method for Assigning Tags to Control Instruction Processing in a Superscalar Processor
System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor
Selective Power-Down for High Performance Cpu/System
System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor
System and Method for Register Renaming
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest.
Feb 7, 1992
From: LENTZ, DEREK J.; LAU, TE-LI
To: S-MOS SYSTEMS
Reel/Frame 006154/0548 →
Assignment of Assignors Interest.
Mar 31, 1992
From: JOHNSON, ANDERS R.
To: S-MOS SYSTEMS, INC.
Reel/Frame 006076/0063 →
Assignment of Assignors Interest.
Apr 8, 1992
From: LIN, CHONG M.; CHUANG, TATAO; LONG, TRAN; HOANG, HY
To: S-MOS SYSTEMS, INC.
Reel/Frame 006081/0071 →
Assignment of Assignors Interest.
May 22, 1992
From: DODSON, JEFFREY M.; CHENG, CHRISTOPHER T.
To: S MOS SYSTEMS, INC.
Reel/Frame 006205/0680 →
Assignment of Assignors Interest.
May 28, 1992
From: S MOS SYSTEMS, INC.
To: SEIKO EPSON CORPORATION, A CORP. OF JAPAN
Reel/Frame 006136/0960 →
Assignment of Assignors Interest.
May 29, 1992
From: LIN, CHONG M.
To: S MOS SYSTEMS, INC.
Reel/Frame 006153/0113 →
Assignment of Assignors Interest.
Jun 1, 1992
From: LENTZ, DEREK J.
To: S MOS SYSTEMS, INC.
Reel/Frame 006153/0900 →
Assignment of Assignors Interest.
Jun 30, 1992
From: TRUONG, HO D
To: S MOS SYSTEMS, A CA CORP.
Reel/Frame 006172/0026 →
Assignment of Assignors Interest.
Jul 30, 1992
From: MIYAYAMA, YOSHIYUKI; TANG, CHENG-LONG
To: S MOS SYSTEMS, INC.
Reel/Frame 006234/0370 →
Assignment of Assignors Interest.
Aug 7, 1992
From: IADONATO, KEVIN R.; NGUYEN, LE TRONG
To: S MOS SYSTEMS, INC.
Reel/Frame 006176/0302 →
Assignment of Assignor's Interest
Oct 11, 1992
From: LENTZ, DEREK J.; HAGIWARA, YASUAKI; LAU, TE-LI; TANG, CHENG-LONG
To: S-MOS SYSTEMS, INC.
Reel/Frame 006551/0732 →
Assignment of Assignors Interest.
Nov 6, 1992
From: LENTZ, DEREK J.
To: S-MOS SYSTEMS, INC.
Reel/Frame 006302/0991 →
Assignment of Assignors Interest.
Nov 9, 1992
From: ALLEGRUCCI, JEAN D.; LENTZ, DEREK J.; POOLE, GLENN C.
To: S MOS SYSTEMS, INC.
Reel/Frame 006302/0125 →
Assignment of Assignors Interest.
Nov 27, 1992
From: LENTZ, DEREK J.; KOSMAL, DAVID R.; POOLE, GLENN C.
To: S MOS SYSTEMS, INC.
Reel/Frame 006314/0440 →
Assignment of Assignors Interest.
Mar 16, 1993
From: LENTZ, DEREK J.; YAP, KIAN-CHIN
To: S-MOS SYSTEMS, INC.
Reel/Frame 006499/0060 →
Assignment of Assignor's Interest
Jun 9, 1993
From: IADONATO, KEVIN R.; DEOSARAN, TREVOR A.
To: S-MOS SYSTEMS, INC.
Reel/Frame 006692/0950 →
Assignment of Assignor's Interest
Nov 2, 1993
From: GARG, SANJIV
To: S-MOS SYSTEMS, INC.
Reel/Frame 006748/0305 →
Assignment of Assignor's Interest
Dec 27, 1993
From: LENTZ, DEREK; YOUNG, LINLEY
To: S-MOS SYSTEMS, INC.
Reel/Frame 006818/0015 →
Assignment of Assignor's Interest
Apr 4, 1994
From: IADONATO, KEVIN R.; DEOSARAN, TREVOR A.; GARG, SANJIV
To: S-MOS SYSTEMS, INC.
Reel/Frame 006958/0423 →
Assignment of Assignor's Interest
Sep 19, 1994
From: S-MOS SYSTEMS, INC.
To: SEIKO EPSON CORPORATION
Reel/Frame 007133/0724 →
Assignment of Assignor's Interest
Nov 18, 1994
From: LENTZ, DEREK J.
To: S-MOS SYSTEMS, INC.
Reel/Frame 007313/0768 →
Assignment of Assignor's Interest
Apr 26, 1995
From: S-MOS SYSTEMS, INC.
To: SEIKO EPSON CORPORATION
Reel/Frame 007436/0333 →
Assignment of Assignor's Interest
Sep 20, 1995
From: S MOS SYSTEMS INC.
To: SEIKO EPSON CORPORATION
Reel/Frame 007641/0183 →
Assignment of Assignor's Interest
Dec 22, 1995
From: S-MOS SYSTEMS, INC.
To: SEIKO EPSON CORPORATION
Reel/Frame 007759/0848 →
Assignment of Assignor's Interest
Sep 3, 1996
From: S-MOS SYSTEMS, INC.
To: SEIKO EPSON CORPORATION
Reel/Frame 008111/0903 →