System and method for handling exceptions and branch mispredictions in a superscalar microprocessor
View Patent ↗An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.
1. A method for handling an exception in a superscalar microprocessor configured to execute a group of instructions, the group of instructions having a predefined program order, the method comprising:
(a) executing a subset of instructions from the group of instructions in an out-of-order fashion with respect to the program order;
(b) storing each result generated in step (a) in a static location in a buffer, wherein the location of the instruction for which the result was generated determines the static location;
(c) detecting an exception; and
(d) responsive to detecting the exception:
(i) suspending out-of-order execution,
(ii) retiring each result stored in step (b) that is the result of an instruction that precedes the instruction that caused the exception in the program order, wherein retiring a result comprises associating the result with a corresponding location in an array, wherein the array includes a plurality of locations referenced to provide execution results of instructions that have been retired, and
(iii) resuming out-of-order execution, wherein resuming out-of-order execution comprises overwriting non-retired results stored in the buffer.
2. The method of claim 1 , wherein step (d)(ii) comprises approximately simultaneously associating multiple results with respective locations in the array.
3. The method of claim 1 , wherein step (d)(ii) comprises concurrently associating multiple results with respective locations in the array.
4. The method of claim 1 , wherein step (d)(ii) comprises associating, substantially in parallel, multiple results with respective locations in the array.
5. The method of claim 1 , further comprising:
associating a unique address with each instruction in the group of instructions.
6. The method of claim 5 , wherein the associating step comprises approximately simultaneously associating multiple unique addresses with respective instructions in the group of instructions.
7. The method of claim 5 , wherein the associating step comprises concurrently associating multiple unique addresses with respective instructions in the group of instructions.
8. The method of claim 5 , wherein the associating step comprises associating, substantially in parallel, multiple unique addresses with respective instructions in the group of instructions.
9. The method of claim 5 , wherein each instruction in the group of instructions specifies a respective location in the array; and
wherein the associating step comprises associating a unique address with each instruction in the group of instructions independent of the respective location in the array specified in each instruction in the group of instructions.
10. The method of claim 5 , wherein each instruction in the group of instructions specifies a respective location in the array; and
wherein the associating step comprises associating a unique address with each instruction in the group of instructions without regard to the respective location in the array specified in each instruction in the group of instructions.
11. The method of claim 5 , wherein each instruction in the group of instructions specifies a respective location in the array;
wherein the associating step comprises associating a first unique address with a first instruction specifying a first location in the array and associating a second unique address with a second instruction specifying a second location in the array; and
wherein the first location in the array and the second location in the array are different.
12. The method of claim 1 wherein step (b) comprises storing each result generated in step (a) in a corresponding static location in an index-addressable buffer.
13. A method for handling a branch misprediction in a superscalar microprocessor configured to execute a group of instructions, the group of instructions having a predefined program order, the method comprising:
(a) executing a subset of instructions from the group of instructions in an out-of-order fashion with respect to the program order;
(b) storing each result generated in step (a) in a corresponding static location in a buffer, wherein the location of the instruction for which the result was generated determines the static location;
(c) detecting a mispredicted branch; and
(d) responsive to detecting the mispredicted branch:
(i) suspending out-of-order execution,
(ii) retiring each result stored in step (b) that is the result of an instruction that precedes the first instruction in the mispredicted branch in the program order, wherein retiring a result comprises associating the result with a corresponding location in an array, wherein the array includes a plurality of locations referenced to provide execution results of instructions that have been retired, and
(iii) resuming out-of-order execution, wherein resuming out-of-order execution comprises overwriting non-retired results stored in the buffer.
14. The method of claim 13 , wherein step (d)(ii) comprises approximately simultaneously associating multiple results with respective locations in the array.
15. The method of claim 13 , wherein step (d)(ii) comprises concurrently associating multiple results with respective locations in the array.
16. The method of claim 13 , wherein step (d)(ii) comprises associating, substantially in parallel, multiple results with respective locations in the array.
17. The method of claim 13 , further comprising:
associating a unique address with each instruction in the group of instructions.
18. The method of claim 17 , wherein the associating step comprises approximately simultaneously associating multiple unique addresses with respective instructions in the group of instructions.
19. The method of claim 17 , wherein the associating step comprises concurrently associating multiple unique addresses with respective instructions in the group of instructions.
20. The method of claim 17 , wherein the associating step comprises associating, substantially in parallel, multiple unique addresses with respective instructions in the group of instructions.
21. The method of claim 17 , wherein each instruction in the group of instructions specifies a respective location in the array; and
wherein the associating step comprises associating a unique address with each instruction in the group of instructions independent of the respective location in the array specified in each instruction in the group of instructions.
22. The method of claim 17 , wherein each instruction in the group of instructions specifies a respective location in the array; and
wherein the associating step comprises associating a unique address with each instruction in the group of instructions without regard to the respective location in the array specified in each instruction in the group of instructions.
23. The method of claim 17 , wherein each instruction in the group of instructions specifies a respective location in the array;
wherein the associating step comprises associating a first unique address with a first instruction specifying a first location in the array and associating a second unique address with a second instruction specifying a second location in the array; and
wherein the first location in the array and the second location in the array are different.
24. The method of claim 13 wherein step (b) comprises storing each result generated in step (a) in a corresponding static location in an index-addressable buffer.