Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
View Patent ↗An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.
1. An integrated structure layout for an instruction execution unit of an integrated circuit chip, comprising:
a row of data dependency comparator blocks, wherein each data dependency comparator block is configured to compare at least one source operand address of a first instruction to a destination operand address of a second instruction and to output data dependency information; and
a tag assignment logic block coupled to the data dependency comparator blocks to receive the data dependency information, wherein the tag assignment block is positioned approximately at the center of the row of data dependency comparator blocks to conserve area on the integrated circuit chip, and wherein the tag assignment logic block outputs tag information identifying an address in a register file responsive to receiving the data dependency information.
2. The integrated structure layout of claim 1 , wherein each data dependency comparator block receives at least one source operand address of an instruction in a group of multiple instructions.
3. The integrated structure layout of claim 2 , wherein each data dependency comparator block receives a destination operand address of the instruction in a group of multiple instructions.
4. The integrated structure layout of claim 1 , wherein each data dependency comparator block is configured to compare at least one source operand address of a first instruction to a destination operand address of a second instruction.
5. The integrated structure layout of claim 4 , wherein the second instruction precedes the first instruction in a predefined program order.
6. The integrated structure layout of claim 1 , wherein each data dependency comparator block is configured to compare two source operand addresses of a first instruction to a destination operand address of a second instruction.
7. The integrated structure layout of claim 1 , wherein the tag assignment logic block receives at least one source operand address and a destination operand address.
8. The integrated structure layout of claim 1 , further comprising:
a register file port multiplexer coupled to the tag assignment logic block to receive the tag information and to pass the tag information to address ports of the register file.
9. The integrated structure layout of claim 8 , wherein the data dependency comparator blocks, the tag assignment logic block and the register file port multiplexer comprise a register renaming circuit that permits out-of-order issuance of multiple instructions.