IP Library Granted Patent US 7,307,293
Granted Patent B2
US 7,307,293 · App. 10/426,930 · Granted Dec 11, 2007

Direct-connect integrated circuit signaling system for bypassing intra-substrate printed circuit signal paths

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Quick Facts
Patent No.
US 7,307,293
App. No.
10/426,930
Granted
Dec 11, 2007
Kind
B2
Abstract

A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above the printed circuit board.

Claims (26)

1. A signaling system comprising:

a printed circuit board;

a first integrated circuit package disposed on the printed circuit board;

a second integrated circuit package disposed on the printed circuit board;

a superstructure mounted above the first integrated circuit package and the second integrated circuit package; and

a first plurality of electric signal conductors coupled to the superstructure, the plurality of signal conductors each having a first end electrically coupled with a corresponding terminal of the first integrated circuit package and a second end electrically coupled with a corresponding terminal of the second integrated circuit package.

2. The signaling system of claim 1 wherein the superstructure is secured to the printed circuit board.

3. The signaling system of claim 1 wherein a plurality of holes are formed in the superstructure, and wherein a respective plurality of posts are oriented within the holes coupling the superstructure to the printed circuit board.

4. The signaling system of claim 1 wherein the at least a portion of at least one of the electric signal conductors is secured to the printed circuit board.

5. The signaling system of claim 3 wherein the posts are configured to removably secure the superstructure to the printed circuit board.

6. The signaling system of claim 1 wherein the first plurality of electric signal conductors comprises a plurality of conductive traces disposed on a surface of the superstructure.

7. The signaling system of claim 1 wherein the first plurality of electric signal conductors are of substantially equal length.

8. The signaling system of claim 1 wherein the first integrated circuit package is configured to transmit or receive skew-sensitive signals through at least some of the first select terminals.

9. The signaling system of claim 1 wherein the first integrated circuit package comprises a substrate and an integrated circuit die disposed on the substrate.

10. The signaling system of claim 9 wherein the first integrated circuit package further comprises a plurality of conductive traces disposed on the substrate, and a first plurality of terminals extending from a plurality of conductive traces on the substrate.

11. The signaling system of claim 10 wherein at least some of the first plurality of terminals comprise a protruding-finger electrical contact shape.

12. The signaling system of claim 11 wherein the integrated circuit die is disposed on a first surface of the substrate and wherein the plurality of conductive traces extend end-to-end along the first surface of the substrate.

13. The signaling system of claim 1 wherein the first and second integrated circuit packages are disposed on a same surface of the printed circuit board.

14. The signaling system of claim 1 wherein the printed circuit board includes a conductive structure coupled to a supply voltage terminal of the first integrated circuit package.

15. The signaling system of claim 9 wherein the first integrated circuit package further comprises a plurality of conductive traces disposed on the substrate and coupled between the first integrated circuit die and at least some of the plurality of electric signal conductors.

16. The signaling system of claim 15 wherein the integrated circuit die is disposed on a first surface of the substrate and wherein the plurality of conductive traces extend end-to-end along the first surface of the substrate.

17. The signaling system of claim 1 , wherein the superstructure further comprises a second plurality of electrical signal paths having a first end coupled to a third integrated circuit package.

18. The signaling system of claim 17 , wherein second ends of the second plurality of electrical signal paths are respectively coupled to signal paths from the first plurality of signal paths to form a multi-drop signal path.

19. The signaling system of claim 18 , wherein second ends of the second plurality of electrical paths are coupled to a fourth integrated circuit package.

20. The signaling system of claim 1 wherein the superstructure is aligned with the printed circuit board.

21. The signal system of claim 3 wherein a portion of the superstructure proximate each hole is in contact with the printed circuit board.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2010
From: TECHNOLOGY PROPERTIES LIMITED
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 025105/0596 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2010
From: INTERCONNECT PORTFOLIO, LLC; INTELLASYS BEC LIMITED; TECHNOLOGY PROPERTIES LIMITED
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 025105/0634 →
LICENSE Recorded Mar 4, 2009
From: INTERCONNECT PORTFOLIO LLC
To: TECHNOLOGY PROPERTIES LIMITED LLC
Reel/Frame 022343/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2008
From: NOVIAS LLC
To: INTERCONNECT PORTFOLIO, LLC
Reel/Frame 021861/0127 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2008
From: HOLDERS, SECURE NOTE; ANDERSON, DAN; FJELSTAD, JOE; GRUNDY, KEVIN; GRUNDY, LAWRENCE; STEPOVICH, MATT
To: NOVIAS, LLC
Reel/Frame 021744/0512 →
FORECLOSURE BY SECURE NOTE HOLDERS Recorded Aug 7, 2008
From: SILICON PIPE, INC.
To: SECURE NOTE HOLDERS: DAN ANDERSON, JOSEPH FJELSTAD, KEVIN GRUNDY, LAURANCE GRUNDY, MATT STEPOVICH
Reel/Frame 021380/0276 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2003
From: FJELSTAD, JOSEPH C.; SEGARAM, PARA K.; HABA, BELGACEM
To: SILICON PIPE, INC.
Reel/Frame 014318/0775 →