Semiconductor device, display device, and signal transmission system
View Patent ↗A display device includes a plurality of data drivers which are cascade-connected, and prevents variation of the duty ratio of a signal caused by accumulation of errors. In each of the plurality of data drivers: a first input circuit receives a first signal supplied from outside; a second input circuit receives a second signal supplied from outside, in response to the first signal received by the first input circuit; a signal processing circuit performs signal processing based on the second signal received by the second input circuit; a first output circuit inverts the first signal received by the first input circuit, and outputs the inverted first signal; and a second output circuit delays the second signal received by the second input circuit, by a predetermined amount, and outputs the delayed second signal.
1. A semiconductor device comprising:
a first input circuit which receives only one clock signal supplied from outside;
a second input circuit which receives a data signal supplied from outside, in response to said clock signal received by said first input circuit;
a signal processing circuit which performs signal processing based on said data signal received by said second input circuit;
a first output circuit which inverts said clock signal received by said first input circuit, and outputs the inverted clock signal; and
a second output circuit which delays said data signal received by said second input circuit by a half cycle of the clock signal, and outputs the delayed data signal only in response to said clock signal,
wherein said second output circuit delays said data signal by using a latch circuit, and
wherein said data signal carries a pair of information pieces at positions corresponding to a leading edge and a trailing edge of said clock signal, said signal processing circuit captures a preceding one of said pair of information pieces from the data signal after said preceding one of said pair of information pieces is output from a delay circuit, and a following one of said pair of information pieces from the data signal before said following one of said pair of information pieces is input to said delay circuit.
2. The semiconductor device according to claim 1 , further comprising,
a third input circuit which receives a start signal indicating capture of said data signal, and
a third output circuit which delays said start signal received by said third input circuit, by a number of cycles of said clock signal which are necessary for capture of said data signal.
3. The semiconductor device according to claim 1 , wherein at least one of said first and second output circuits delays said data signal by using a delay line.
4. A display device comprising:
a display panel;
a gate driver which drives gate bus lines of said display panel; and
a plurality of data drivers which are cascade-connected, and drive data bus lines of said display panel;
each of said plurality of data drivers includes,
a first input circuit which receives only one clock signal supplied from a preceding stage,
a second input circuit which receives a data signal supplied from the preceding stage, in response to said clock signal received by said first input circuit,
a signal processing circuit which performs signal processing based on said data signal received by said second input circuit,
a first output circuit which inverts said clock signal received by said first input circuit, and outputs the inverted clock signal, and
a second output circuit which delays said data signal received by said second input circuit by a half cycle of the clock signal, and outputs the delayed data signal only in response to said clock signal,
wherein said second output circuit delays said data signal by using a latch circuit, and
wherein said data signal carries a pair of information pieces at positions corresponding to a leading edge and a trailing edge of said clock signal, said signal processing circuit captures a preceding one of said pair of information pieces from the data signal after said preceding one of said pair of information pieces is output from a delay circuit, and a following one of said pair of information pieces from the data signal before said following one of said pair of information pieces is input to said delay circuit.
5. The display device according to claim 4 , further comprising,
a third input circuit which receives a start signal indicating capture of said data signal, and
a third output circuit which delays said start signal received by said third input circuit, by a number of cycles of said clock signal which are necessary for capture of said data signal.
6. The display device according to claim 4 , wherein at least one of said first and second output circuits delays said data signal by using a delay line.
7. A signal transmission system including a plurality of semiconductor devices which are cascade-connected, and sequentially transmitting inputted signals, wherein each of said plurality of semiconductor devices includes:
a first input circuit which receives only one clock signal supplied from a preceding stage;
a second input circuit which receives a data signal supplied from the preceding stage, in response to said clock signal received by said first input circuit;
a signal processing circuit which performs signal processing based on said data signal received by said second input circuit;
a first output circuit which inverts said clock signal received by said first input circuit, and outputs the inverted clock signal; and
a second output circuit which delays said data signal received by said second input circuit by a half cycle of the clock signal, and outputs the delayed data signal only in response to said clock signal,
wherein said second output circuit delays said data signal by using a latch circuit, and
wherein said data signal carries a pair of information pieces at positions corresponding to a leading edge and a trailing edge of said clock signal, said signal processing circuit captures a preceding one of said pair of information pieces from the data signal after said preceding one of said pair of information pieces is output from a delay circuit, and a following one of said pair of information pieces from the data signal before said following one of said pair of information pieces is input to said delay circuit.