Method of manufacturing a semiconductor device
View Patent ↗To ensure the connectability of wiring lines in a semiconductor device having terminals or reservoirs, plural terminals of a cell, which constitutes the semiconductor device, are each formed in a shape having a length corresponding to two or more lattice points. The terminals are arranged so that one or more lattice points are interposed between adjacent terminals. Among the terminals, as to terminals that are adjacent to each other in their shorter direction, it is allowable for them to partially overlap each other in their shorter direction. In this state, second-layer wiring lines are connected to the terminals via through holes, whereby reservoirs can be generated at the terminals, respectively.
1. A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming an N-type transistor and a P-type transistor in an intra cell region, so as to comprise a function cell;
(b) forming an intra cell wiring layer connecting said N-type transistor and P-type transistor in an intra cell region;
(c) forming a terminal pattern in a first wiring layer along a first direction, said terminal pattern being connected by a via to said intra cell wiring layer; and
(d) forming a wiring line in a second wiring layer different from the first wiring layer along a second direction, the wiring line being connected to the terminal pattern through a hole,
wherein said terminal pattern shares two or more lattice points on the first wiring layer, and further comprising:
(e) forming a surplus portion at the terminal pattern in a position where the hole is formed on the same wiring layer as the terminal pattern, and wherein the surplus portion is provided so as to extend in a shorter direction of the terminal pattern or in a longer direction of the terminal pattern by a length not larger than one lattice point from a plane center of said hole.
2. A method according to claim 1 , wherein the terminal pattern has a rectangular shape.
3. A method according to claim 1 , wherein a plurality of terminal patterns are formed, at least one thereof being said terminal pattern sharing two or more lattice points on the first wiring layer; and wherein the plurality of terminal patterns are arranged such that one or more lattice points are interposed between adjacent said terminal patterns.
4. A method according to claim 1 , wherein the first direction and the second direction are different from each other.
5. A method according to claim 4 , wherein the first direction and the second direction are perpendicular to each other.
6. A method according to claim 1 , wherein when another wiring line or another terminal pattern is present at a position adjacent longitudinally to the terminal pattern in a same layer as the terminal pattern, the surplus portion is provided so as to extend in the shorter direction of the terminal pattern, with a length not larger than one lattice point from a plane center of the hole.