Timing based scan chain implementation in an IC design

1. For use with a timing database, a computer implemented process for electronic design automation comprising:

receiving a netlist including at least one first scan cell triggered by a first clock triggering edge and at least one second scan cells triggered by a second clock triggering edge;

receiving from the timing database clock timing information that indicates a source clock trigger time (CTT) of the first clock triggering edge and that indicates a source CTT of the second clock triggering edge; and

ordering each at least one first scan cell and each at least one second scan cell relative to each other in a design in descending order of the respective source CTTs of the respective first and second triggering clock edges.

2. The process of claim 1 ,

wherein the first clock triggering edge is a triggering edge of a first periodic clock signal; and

wherein the second clock triggering edge is a triggering edge of a second periodic clock signal.

3. The process of claim 1 ,

wherein the first clock triggering edge and the second clock triggering edge are parts of one periodic clock signal.

4. The process of claim 1 further including:

stitching directly each of the at least one first scan cell and each of the at least one second scan cell in a scan chain in the design.

5. The computer implemented process of claim 1 further including:

receiving an HDL description of an integrated circuit design; and

generating the netlist based upon the HDL description.

6. The computer implemented process of claim 5 ,

wherein generating the netlist includes insertion of scan cells.

7. The process of claim 1 ,

wherein receiving the netlist includes receiving a netlist that also includes at least one third scan cell triggered by a third clock triggering edge;

wherein receiving from the timing database includes receiving clock timing information that indicates a source CTT of the third clock triggering edge; and

wherein ordering includes ordering each at least one first scan cell and each at least one second scan cell and each at least one third scan cell relative to each other in a design in descending order of the respective source CTTs of the respective first, second and third triggering clock edges.

8. The process of claim 7 ,

wherein the first clock triggering edge is a triggering edge of a first periodic clock signal;

wherein the second clock triggering edge is a triggering edge of the first periodic clock signal;

wherein the third clock triggering edge is a triggering edge of a second periodic clock signal; and

wherein each of the at least one first scan cell and each of the at least one second scan cell and each of the at least one third scan cell are directly stitched together in a scan chain in the design.

9. The process of claim 7 ,

wherein the first clock triggering edge is a first triggering edge of a first periodic clock signal;

wherein the second clock triggering edge is a second triggering edge of the first periodic clock signal;

wherein the third clock triggering edge is a triggering edge of a second periodic clock signal.

10. The process of claim 7 further including:

stitching directly each of the at least one first scan cell and each of the at least one second scan cell and each of the at least one third scan cell in a scan chain in the design.

11. The process of claim 1 ,

wherein receiving the netlist includes receiving a netlist that also includes at least one third scan cell triggered by a third clock triggering edge and includes at least one fourth scan cell triggered by a fourth clock triggering edge;

wherein receiving from the timing database includes receiving clock timing information that indicates a source CTT of the third clock triggering edge and indicates a source CTT of the fourth clock triggering edge; and

wherein ordering includes ordering each at least one first scan cell and each at least one second scan cell and each at least one third scan cell and each at least one fourth scan cell relative to each other in a design in descending order of the respective source CTTs of the respective first, second, third and fourth triggering clock edges.

12. The process of claim 11 ,

wherein the first clock triggering edge is a first triggering edge of a first periodic clock signal;

wherein the second clock triggering edge is a second triggering edge of the first periodic clock signal;

wherein the third clock triggering edge is a first triggering edge of a second periodic clock signal; and

wherein the fourth clock triggering edge is a second triggering edge of the second periodic clock signal.

13. The process of claim 11 ,

wherein the first clock triggering edge is a triggering edge of a first periodic clock signal;

wherein the second clock triggering edge is a triggering edge of the first periodic clock signal;

wherein the third clock triggering edge is a first triggering edge of a second periodic clock signal;

wherein the fourth clock triggering edge is a second triggering edge of the second periodic clock signal; and

wherein each of the at least one first scan cell and each of the at least one second scan cell and each of the at least one third scan cell and each of the at least one fourth scan cell are directly stitched together in a scan chain in the design.

14. The process of claim 1 further including:

stitching directly each of the at least one first scan cell and each of the at least one second scan cell and each of the at least one third scan cell and each of the at least one fourth scan cell in a scan chain in the design.

15. The process of claim 1 ,

wherein the first clock triggering edge is a triggering edge of a first periodic clock signal;

wherein the second clock triggering edge is a triggering edge of a second periodic clock signal; and

wherein each of the at least one first scan cell and each of the at least one second scan cell are directly stitched together in a scan chain in the design.

16. For use with a timing database, a computer implemented process for electronic design automation comprising:

receiving a netlist including at least one first scan cell triggered by a first clock triggering edge and at least one second scan cells triggered by a second clock triggering edge;

receiving from the timing database clock timing information that indicates instance clock trigger time (CTT) of the first clock triggering edge at each of the at least one first start cell and that indicates instance CTT of the second clock triggering edge at each of the at least one second scan cell; and

ordering each at least one first scan cell and each at least one second scan cell relative to each other in a design in descending order of instance CTTs.

17. The process of claim 16 ,

wherein the first clock triggering edge is a triggering edge of a first periodic clock signal; and

wherein the second clock triggering edge is a triggering edge eta second periodic clock signal.

18. The process of claim 16 ,

wherein the first clock triggering edge and the second clock triggering edge are parts of one periodic clock signal.

19. The process of claim 16 further including:

stitching directly each of the at least one first scan cell and each of the at least one second scan cell in a scan chain in the design.

20. The computer implemented process of claim 16 further including;

receiving an HDL description of an integrated circuit design; and

generating the netlist based upon the HDL description.

21. The computer implemented process of claim 20 ,

wherein generating the netlist includes insertion of scan cells.

22. The process of claim 16 ,

wherein receiving the netlist includes receiving a netlist that also includes at least one third scan cell triggered by a third clock triggering edge;

wherein receiving from the timing database includes receiving clock timing information that indicates instance CTT of the third clock triggering edge at each of the at least one third scan cell; and

wherein ordering includes ordering each at least one first scan cell and each at least one second scan cell and each at least one third scan cell relative to each other in a design in descending order of instance CTTs.

23. The process of claim 22 ,

wherein the first clock triggering edge is a first triggering edge of a first periodic clock signal;

wherein the second clock triggering edge is a second triggering edge of the first periodic clock signal;

wherein the third clock triggering edge is a triggering edge of a second periodic clock signal.

24. The process of claim 22 further including:

stitching directly each of the at least one first scan cell and each of the at least one second scan cell and each of the at least one third scan cell in a scan chain in the design.

25. The process of claim 16 ,

wherein receiving the netlist includes receiving a netlist that also includes at least one third scan cell triggered by a third clock triggering edge and includes at least one fourth scan cell triggered by a fourth clock triggering edge;

wherein receiving from the timing database includes receiving clock timing information that indicates instance CTT of the third clock triggering edge at each of the at least one third scan cell and receiving clock timing information that indicates instance CTT of the fourth clock triggering edge at each of the at least one fourth scan cell; and

wherein ordering includes ordering each at least one first scan cell and each at least one second scan cell and each at least one third scan cell and each at least one fourth scan cell relative to each other in a design in descending order of instance CTTs.

26. The process of claim 25 ,

wherein the first clock triggering edge is a first triggering edge of a first periodic clock signal;

wherein the second clock triggering edge is a second triggering edge of the first periodic clock signal;

wherein the third clock triggering edge is a first triggering edge of a second periodic clock signal; and

wherein the fourth clock triggering edge is a second triggering edge of the second periodic clock signal.

27. The process of claim 16 further including:

stitching directly each of the at least one first scan cell and each of the at least one second scan cell and each of the at least one third scan cell and each of the at least one fourth scan cell in a scan chain in the design.

28. For use with a timing database, a computer implemented process for electronic design automation comprising:

receiving a netlist including multiple scan cells in which a first set of the multiple scan cells is triggered by a first triggering clock edge and a second set of the multiple scan cells is triggered by a second triggering clock edge;

receiving from the timing database clock timing information that indicates a source clock trigger time (CTT) of the first clock triggering edge and that indicates a source CTT of the second clock triggering edge;

receiving from the timing database clock timing information that respectively indicates instance CTTs of the first triggering clock edge at respective scan cells of the first set and that respectively indicates instance CTTs of the second triggering dock edge at respective scan cells of the second set; and

ordering the multiple scan cells in a design so that the scan cells are ordered relative to each other in descending order of source CTTs and so that scan cells are further ordered relative to each other in descending order of arrival time of their instance CTTs.

29. The process of claim 28 ,

wherein the first clock triggering edge is a triggering edge of a first periodic clock signal; and

wherein the second clock triggering edge is a triggering edge of a second periodic clock signal.

30. The process of claim 28 ,

wherein the first clock triggering edge second clock triggering edge are parts of one periodic clock signal.

31. The process of claim 28 further including:

stitching directly each of the at least one first scan cell and each of the at least one second scan cell in a scan chain in the design.

32. The computer implemented process of claim 28 further including;

receiving an HDL description of an integrated circuit design; and

generating the netlist based upon the HDL description.

33. The computer implemented process of claim 32 ,

wherein generating the netlist includes insertion of scan cells.

34. The process of claim 28 ,

wherein receiving the netlist includes receiving a netlist that also includes a third set of the multiple scan cells triggered by a third triggering clock edge; and

wherein receiving from the timing database includes receiving clock timing information that indicates a source clock trigger time of the third clock triggering edge.

35. The process of claim 34 ,

wherein the first clock triggering edge is a first triggering edge of a first periodic clock signal;

wherein the second clock triggering edge is a second triggering edge of the first periodic clock signal;

wherein the third clock triggering edge is a triggering edge of a second periodic clock signal.

36. The process of claim 34 further including:

stitching directly each of the at least one first scan cell and each of the at least one second scan cell and each of the at least one third scan cell in a scan chain in the design.

37. The process of claim 28 ,

wherein receiving the netlist includes receiving a netlist that also includes a third set of the multiple scan cells triggered by a third triggering clock edge and that includes a fourth set of the multiple scan cells triggered by a fourth triggering clock edge; and

wherein receiving from the timing database includes receiving clock timing information that indicates a source CTT of the third clock triggering edge and that indicates a soiree CTT of the fourth clock triggering edge; and

wherein receiving from the timing database further includes receiving clock timing information that indicates instance CTTs of the third triggering clock edge at respective scan cells of the third set and that indicates instance CTTs of the fourth triggering clock edge at respective scan cells of the fourth set.

38. The process of claim 37 ,

wherein the first clock triggering edge is a first triggering edge of a first periodic clock signal;

wherein the second clock triggering edge is a second triggering edge of the first periodic clock signal;

wherein the third clock triggering edge is a first triggering edge of a second periodic clock signal; and

wherein the fourth clock triggering edge is a second triggering edge of the second periodic clock signal.

39. The process of claim 28 further including:

stitching directly each of the at least one first scan cell and each of the at least one second scan cell and each of the at least one third scan cell and each of the at least one fourth scan cell in a scan chain in the design.