Scan insertion with bypass login in an IC design
A computer implemented process of inserting enhanced scan bypass in relation to a bypassed block in an integrated circuit design comprising: receiving an HDL description of the circuit design; wherein the HDL description includes a port specification HDL instruction that specifies port properties of a bypassed block; wherein the HDL description includes an enhanced bypass HDL instruction that specifies how many scan cells to provide per port of the bypassed block in a scan bypass circuit that bypasses the bypassed block; wherein the bypass HDL instruction includes a user-selectable option of at least zero or one or two scan cells per port; in response to the specification HDL instruction and the enhanced bypass HDL instruction, automatically generating a netlist portion that includes scan a bypass circuit that bypasses the bypassed block and that includes the specified number of scan cells per port.
1. A computer implemented process of inserting scan chain bypass circuitry in a scan chain in an integrated circuit design comprising:
receiving an HDL description of the circuit design;
wherein the HDL description includes a scan chain bypass circuitry insertion instruction that specifies how many scan cells to provide in scan bypass circuitry per input/output port pair of a circuit block bypassed by the scan chain;
wherein the scan chain bypass circuitry insertion instruction includes a user-selectable option of at least zero or one or two scan cells per input/output port pair;
in response to the HDL description and the scan chain bypass circuitry insertion instruction, automatically generating a netlist portion that includes the scan chain bypass circuitry that is interconnected in the scan chain and that includes the specified number of scan cells per input/output port pair.
2. The computer implemented process of claim 1 wherein said HDL description comprises a VHDL description.
3. The computer implemented process of claim 1 wherein said HDL description comprises a Verilog description.
4. The computer implemented process of claim 1 wherein said scan bypass circuitry is capable of setting a signal output responsive to a test signal.
5. The computer implemented process of claim 1 ,
wherein the HDL description includes a port specification that specifies port properties of a bypassed block.
6. The computer implemented process of claim 1 ,
wherein the HDL description includes a port specification that specifies input/output port pairs of a block to be bypassed by a scan chain.
7. The computer implemented process of claim 1 ,
wherein the HDL description includes a port specification that specifies which output pins and which output pins of a block to be bypassed by a scan chain are to be subject to the specified number of scan cells per input/output port pair.
8. An article of manufacture comprising:
a computer readable medium encoded with,
an HDL description of a circuit design;
wherein the HDL description includes a scan chain bypass circuitry insertion instruction that specifies how many scan cells to provide in scan bypass circuitry per input/output port pair of a circuit block bypassed by the scan chain;
wherein the scan chain bypass circuitry insertion instruction includes a user-selectable option of at least zero or one or two scan cells per input/output port pair; and
computer program code that automatically generates a netlist portion that includes the scan chain bypass circuitry that includes the specified number of scan cells per input/output port pair in response to the HDL description and the instruction.
9. The article of manufacture of claim 8 , wherein said HDL description comprises a VHDL description.
10. The article of manufacture of claim 8 , wherein said HDL description comprises a Verilog description.
11. The article of manufacture of claim 8 , wherein said scan bypass circuitry is capable of setting a signal output responsive to a test signal.
12. The article of manufacture of claim 8 ,
wherein the HDL description includes a port specification that specifies port properties of a bypassed block.
13. The article of manufacture of claim 8 ,
wherein the HDL description includes a port specification that specifies input/output port pairs of a block to be bypassed by a scan chain.
14. The article of manufacture of claim 8 ,
wherein the HDL description includes a port specification that specifies which input pins and which output pins of a block to be bypassed by a scan chain are to be subject to the specified number of scan cells per input/output port pair.