Multi-level integrated circuit for wide-gap substrate bonding
View Patent ↗An integrated circuit includes a substrate having an etched surface and a non-etched surface. The etched surface contains circuit elements and the non-etched surface contains a bonding surface. The non-etched surface is located at a predetermined height from the etched surface. Bonding this integrated circuit with another substrate creates a wide-gap between the substrates that is preferably evacuated and hermetically sealed.
1. A method for creating an integrated circuit, comprising the steps of:
patterning a hard mask over a portion of a substrate;
etching a trench within the substrate to a desired depth thereby forming inclined sidewalls from a first surface of the etched substrate to a second surface covered by the hard mask;
etching along the <311> crystalline plane of the substrate along at least a portion of the inclined sidewalls that interface to the second surface;
removing the hard mask; and
forming circuit elements using semiconductor processing steps on the first surface.
2. The method of claim 1 , further comprising the steps of:
forming a dielectric layer extending from the circuit elements to the second surface; and
forming a set of conductive traces on the dielectric layer from the circuit elements to the second surface.
3. The method of claim 1 wherein the desired depth is about 2 microns to about 400 microns.
4. The method of claim 1 wherein the step of etching the trench is performed using a wet chemical etch.
5. The method of cIaim 1 further comprising the step of:
forming a seal around the outer periphery of the second surface.
6. A method for creating a micro-machined system comprising the steps of:
bonding a first integrated circuit created by the method of claim 1 with a substrate.
7. The method of claim 6 wherein the bonding of the first integrated circuit with the substrate further comprises the step of forming electrical interconnections between the circuit elements of the first integrated circuit and the substrate.
8. The method of claim 5 , wherein the substrate is processed by the method of claim 1 to form a second integrated circuit.
9. A method for creating a gradual incline for improved step coverage, comprising the steps of:
masking a <100> substrate surface with a hard mask;
patterning the hard mask to define an opening within the hard mask;
etching the <100> substrate surface to create an inclined angled profile along the <111> orientation of the substrate;
removing at least a portion of the hard mask to expose a portion of the <100> substrate surface that interfaces with the <111> etched inclined angle profile; and
etching the exposed <100> substrate surface to create a <311> inclined angle profile that is less steep than the <111> inclined angled profile.
10. A method for creating a multi-level substrate comprising the steps of claim 9 .
11. The method of claim 9 wherein the steps of etching the <100> substrate and etching the exposed <100> substrate are performed using tetra-methyl ammonium hydroxide.
12. The method of claim 9 wherein the <111> inclined angle profile is substantially replaced with the <311> inclined angle profile.
13. The method of claim 12 wherein light incident from mask exposure is not reflected from the inclined angle profile onto the substrate surface.
14. The method of claim 9 wherein the improved step coverage allows for deposition of dielectric material on the <311> inclined profile and the <100> substrate without a seam being formed.
15. The method of claim 9 wherein the step of etching the <100> substrate includes etching the <100> substrate to a depth of up to about 400 microns.
16. The method of claim 9 wherein the step of etching the <100> substrate includes etching the <100> substrate more than about 2 microns.