Start detection circuit, stop detection circuit and circuit for the detection of data transmitted according to the IIC protocol

1. A start detection circuit to detect a start condition in a data signal associated with a clock signal according to the IIC protocol, the circuit comprising:

a first detector to produce a first reset signal when a trailing edge of the data signal is detected;

a counter to count pulses of a reference signal when the first reset signal is received, and to produce an enabling signal when the number of pulses counted has reached a predefined number; and

a second detector to store the enabling signal when a trailing edge of the clock signal is detected.

2. A circuit according to claim 1 , also comprising a disabling circuit to stop the counter when the predetermined number is reached.

3. A circuit for the detection of data transmitted according to the IIC protocol, comprising a start detection circuit according to claim 1 , and a stop detection circuit to detect a stop condition on a data signal associated with a clock signal according to the IIC protocol, the circuit comprising a third detector, to produce a stop signal when a leading edge of the data signal is detected after the detection of a leading edge of the clock signal.

4. A start detection circuit to detect a start condition in a data signal associated with a clock signal according to the IIC protocol, the circuit comprising:

a first detector to produce a first reset signal when a trailing edge of the data signal is detected;

a counter to count pulses of a reference signal when the first reset signal is received, and to produce an enabling signal when the number of pulses counted has reached a predefined number; and

a second detector to store the enabling signal when a trailing edge of the clock signal is detected; and

a reset circuit to produce a second reset signal equal to a signal that is the complement of the clock signal and is synchronized with the clock reference signal, said second reset signal being used to reset the first detector and/or the second detector.

5. A start detection circuit to detect a start condition in a data signal associated with a clock signal according to the IIC protocol, the circuit comprising:

a first detector to produce a first reset signal when a trailing edge of the data signal is detected, wherein the first detector comprises a latch circuit comprising a data input connected to a ground of the circuit, a clock input to which the data signal is applied, and a data output at which the first reset signal is produced;

a counter to count pulses of a reference signal when the first reset signal is received, and to produce an enabling signal when a number of pulses counted has reached a predefined number; and

a second detector to store the enabling signal when a trailing edge of the clock signal is detected.

6. A circuit according to claim 5 , wherein the first detector also comprises a gate comprising two data inputs to which the first reset signal and a powering-on signal are applied, and an output connected to a reset input of the counter.

7. A start detection circuit to detect a start condition in a data signal associated with a clock signal according to the IIC protocol, the circuit comprising:

a first detector to produce a first reset signal when a trailing edge of the data signal is detected;

a counter to count pulses of a reference signal when the first reset signal is received, and to produce an enabling signal when the number of pulses counted has reached a predefined number; and

a second detector to store the enabling signal when a trailing edge of the clock signal is detected, wherein the second detector comprises a D-type latch comprising a data input to which the enabling signal is applied and a clock input to which the clock signal is applied.

8. A start detection circuit to detect a start condition in a data signal associated with a clock signal according to the IIC protocol, the circuit comprising:

a first detector to produce a first reset signal when a trailing edge of the data signal is detected;

a counter to count pulses of a reference signal when the first reset signal is received, and to produce an enabling signal when a number of pulses counted has reached a predefined number;

a second detector to store the enabling signal when a trailing edge of the clock signal is detected; and

a disabling circuit to stop the counter when the predetermined number is reached, wherein the disabling circuit comprises a gate comprising two inputs to which the enabling signal and the reference signal are applied respectively, and an output connected to a clock input of the counter.

9. A start detection circuit to detect a start condition in a data signal associated with a clock signal according to the IIC protocol, the circuit comprising:

a first detector to produce a first reset signal when a trailing edge of the data signal is detected;

a counter to count pulses of a reference signal when the first reset signal is received, and to produce an enabling signal when a number of pulses counted has reached a predefined number;

a second detector to store the enabling signal when a trailing edge of the clock signal is detected; and

a reset circuit to produce a second reset signal equal to a signal that is the complement of the clock signal and is synchronized with the clock reference signal, said second reset signal being used to reset the first detector and/or the second detector, wherein the reset circuit comprises a latch circuit comprising a data input to which the clock signal is applied, a clock input to which the reference signal is applied, and an output at which a second reset signal is produced.

10. A circuit according to claim 9 , wherein the reset circuit also comprises a gate comprising two inputs to which the second reset signal and the powering-on signal are applied, and an output connected to a reset input of the first detector and/or to a reset input of the second detector.

11. A stop detection circuit to detect a stop condition on a data signal associated with a clock signal according to the IIC protocol, the circuit comprising a detector, to produce a stop signal when a leading edge of the data signal is detected after the detection of a leading edge of the clock signal, also comprising a reset circuit to produce a second reset signal equal to a signal that is the inverse of the clock signal and synchronized with a reference signal, said second reset signal being used to reset the detector.

12. A circuit according to claim 11 , wherein the detector comprises a latch circuit comprising a data input to which a power supply voltage is applied, a clock input to which the data signal is applied and an output at which a stop signal is produced.

13. A start-detection circuit, comprising:

a first logic circuit operable to detect an edge of a first IIC signal; and

a second logic circuit coupled to the first logic circuit and operable to generate a start signal in response to detecting an edge of a second IIC signal at least a predetermined time after the first logic circuit detects the edge of the first IIC signal, the predetermined time being derived from a reference signal that is independent of the first and second IIC signals.

14. The start-detection circuit of claim 13 wherein:

the first IIC signal comprises an IIC data signal; and

the second IIC signal comprises an IIC clock signal.

15. The start-detection circuit of claim 13 wherein the edges of the first and second IIC signals respectively comprise falling edges.

16. The start-detection circuit of claim 13 wherein:

the second logic circuit comprises a counter and is operable to generate the start signal if the counter has counted to or beyond a predetermined value when the second logic circuit detects the edge of the second IIC signal; and

the first logic circuit is operable to enable the counter in response to detecting the edge of the first IIC signal.

17. The start-detection circuit of claim 13 wherein the first logic circuit comprises a flip-flop having a clock node operable to receive the first IIC signal.

18. A stop-detection logic circuit operable to generate a stop signal in response to detecting an edge of a data signal while a clock signal has a predetermined value, the stop-detection logic circuit further comprising a flip-flop having:

a clock node operable to receive the data signal; and

a reset node operable to receive a reset signal, the reset signal being derived from the clock signal and being synchronized with a second clock signal that is independent of the first clock signal.

19. The stop-detection logic circuit of claim 18 wherein:

the data signal comprises an IIC data signal; and

the clock signal comprises an IIC clock signal.

20. The stop-detection logic circuit of claim 18 wherein:

the edge of the data signal comprises a rising edge; and

the predetermined value comprises a high logic level.

21. An integrated circuit, comprising:

a start-detection circuit, comprising,

a first logic circuit operable to detect an edge of a first IIC signal, and

a second logic circuit coupled to the first logic circuit and operable to generate a start signal in response to detecting an edge of a second IIC signal at least a predetermined time after the first logic circuit detects the edge of the first IIC signal, the predetermined time being derived from a reference signal that is independent of the first and second IIC signals.

22. An integrated circuit, comprising:

a stop-detection logic circuit operable to generate a stop signal in response to detecting an edge of a data signal while a clock signal has a predetermined value, wherein the stop-detection logic circuit further includes a flip-flop having:

a clock node operable to receive the data signal; and

a reset node operable to receive a reset signal, the reset signal being derived from the clock signal and being synchronized with a second clock signal that is independent of the first clock signal.

23. An electronic system, comprising:

a data line operable to carry an IIC data signal;

a clock line operable to carry an IIC clock signal; and

an integrated circuit coupled to the data and clock lines and including,

a start-detection circuit, comprising,

a first logic circuit operable to detect an edge of the IIC data signal, and

a second logic circuit coupled to the first logic circuit and operable to generate a start signal in response to detecting an edge of the IIC clock signal at least a predetermined time after the first logic circuit detects the edge of the IIC data signal, the predetermined time being derived from a reference signal that is independent of the first and second IIC signals.

24. The electronic system of claim 23 wherein the first integrated circuit further comprises a stop-detection circuit operable to generate a stop signal in response to detecting an edge of the IIC data signal while the IIC clock signal has a predetermined value.

25. An electronic system, comprising:

a data line operable to carry a data signal;

a clock line operable to carry a clock signal; and

a first integrated circuit coupled to the data and clock lines and including,

a stop-detection logic circuit operable to generate a stop signal in response to detecting an edge of the data signal while the clock signal has a predetermined value wherein the stop-detection logic circuit further includes a flip-flop having:

a clock node operable to receive the data signal; and

a reset node operable to receive a reset signal, the reset signal being derived from the clock signal and being synchronized with a second clock signal that is independent of the first clock signal.

26. A method, comprising:

detecting an edge of a first IIC signal with a first logic circuit; and

generating a start signal with a second logic circuit in response to detecting an edge of a second IIC signal at least a predetermined time after detecting the edge of the first IIC signal, the predetermined time being derived from a reference signal that is independent of the first and second IIC signals.

27. The method of claim 26 wherein generating the start signal comprises:

counting a number of predetermined intervals between the edge of the first IIC signal and the edge of the second IIC signal; and

generating the start signal only if the number of predetermined intervals equals or exceeds a predetermined value.

28. A method, comprising:

detecting an edge of a data signal with a logic circuit; and

generating a stop signal with the logic circuit if a first clock signal has a predetermined value; and

generating a reset signal derived from the first clock signal, the reset signal being synchronized with the a second clock signal that is independent of the first clock signal.