Strained Fin FETs structure and method
View Patent ↗A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.
1. A fin-type field effect transistor (FinFET) comprising:
a fin having source and drain regions and a channel region between said source and drain regions; and
a strain-inducing layer on only one side of said channel region of said fin.
2. The FinFET in claim 1 , wherein said strain-inducing layer strains said channel region due to differences in crystalline lattice constants of said channel region and said strain-inducing layer.
3. The FinFET in claim 1 , wherein said strain-inducing layer has a sufficient concentration of impurity to produce strain within said channel region to enhance carrier mobility, without producing sufficient dislocations to reduce overall performance of said transistor.
4. The FinFET in claim 1 , wherein said channel region comprises a relaxed silicon and said strain-inducing layer comprises strained silicon germanium.
5. The FinFET in claim 1 , further comprising a first gate on a first side of said channel region of said fin and a second gate on a second side of said channel region of said fin.
6. The FinFET in claim 5 , wherein said first gate is different than said second gate.
7. A fin-type field effect transistor (FinFET) comprising:
a fin having source and drain regions and a channel region between said source and drain regions;
a strain-inducing layer on said channel region of said fin; and
asymmetric gates on opposite sides of said channel region, said asymmetric gates having different conductivity types.
8. The FinFET in claim 7 , wherein said strain-inducing layer strains said channel region due to differences in crystalline lattice constants of said channel region and said strain-inducing layer.
9. The FinFET in claim 7 , wherein said strain-inducing layer has a sufficient concentration of impurity to produce strain within said channel region to enhance carrier mobility, without producing sufficient dislocations to reduce overall performance of said transistor.
10. The FinFET in claim 7 , wherein said channel region comprises a relaxed silicon and said strain-inducing layer comprises strained silicon germanium.
11. The FinFET in claim 7 , wherein said asymmetric gates comprises a first gate having a first impurity concentration on a first side of said channel region of said fin and a second gate having a second impurity concentration on a second side of said channel region of said fin.
12. The FinFET in claim 11 , wherein said asymmetric gates comprising a first gate having a first impurity on a first side of said channel region of said fin and a second gate having a second impurity different than said first impurity on a second side of said channel region of said fin.
13. A silicon-over-insulator (SOI) fin-type effect transistor (FinFET) comprising:
an isolation layer;
a fin on said isolation layer; said fin having source and drain regions and a channel region between said source and drain regions; and
a strain-inducing layer on only one side of said channel region of said fin.
14. The FinFET in claim 13 , wherein said strain-inducing layer strains said channel region due to differences in crystalline lattice constants of said channel region and said strain-inducing layer.
15. The FinFET in claim 13 , wherein said strain-inducing layer has a sufficient concentration of impurity to produce strain within said channel region to enhance carrier mobility, without producing sufficient dislocations to reduce overall performance of said transistor.
16. The FinFET in claim 13 , wherein said channel region comprises a relaxed silicon and said strain-inducing layer comprises strained silicone germanium.
17. The FinFET in claim 13 , further comprising a first gate on a first side of said channel region of said fin and a second gate on a second side of said channel region of said fin.
18. The FinFET in claim 17 , wherein said first gate is different than said second gate.