Configurable voltage controlled oscillator system and method
View Patent ↗A phase lock loop with multiple divider paths is presented herein. The phase lock loop can be used to provide a wide range of frequencies. The phase lock loop can also be used as a portion of a clock multiplier unit or a clock data and recovery unit.
1. A phase lock loop comprising:
a phase detector;
a voltage controlled oscillator connected to the phase detector;
a plurality of divider paths connected to said voltage controlled oscillator;
a multiplexer connected to said plurality of divider paths and said phase detector; and
at least one divider forming a portion of two or more of the plurality of divider paths.
2. The phase lock loop of claim 1 , wherein the voltage controlled oscillator further comprises a ring oscillator.
3. The phase lock loop of claim 1 , further comprising:
a plurality of outputs connected to the divider paths, wherein the outputs provide a corresponding plurality of frequency signals.
4. The phase lock loop of claim 3 , wherein the plurality of frequency signals comprise:
frequency signals for OC- 3 , OC- 12 , OC- 48 , and Gigabit Ethernet.
5. A phase lock loop system for synchronizing an input signal, said phase lock loop system comprising:
a phase detector for comparing phases between the input signal and a feedback signal and providing a control signal, wherein the control signal is dependent on a difference in phase between the input signal and the feedback signal;
a voltage controlled oscillator for generating a frequency signal, wherein the frequency signal is dependent on the control signal;
a plurality of divider paths for dividing the frequency of the frequency signal;
a multiplexer for providing the feedback signal to the phase detector;
at least one divider forming a portion of two or more of the plurality of divider paths.
6. The phase lock loop of claim 5 , wherein the multiplexer selects a particular one of the divider paths, and wherein a signal from the selected divider path is the feedback signal.
7. The phase lock loop of claim 5 , wherein the voltage controlled oscillator further comprises a ring oscillator.
8. The phase lock loop of claim 5 , further comprising:
a plurality of outputs for outputting a corresponding plurality of output frequency signals.
9. The phase lock loop of claim 8 , wherein the plurality of output frequency signals further comprise an OC- 3 signal, an OC- 12 signal, an OC- 48 signal, and a Gigabit Ethernet signal.
10. The phase lock loop of claim 8 , further comprising at least one divider for multiplying the frequency of a particular one of the plurality of output frequency signals.