IP Library Granted Patent US 6,890,851
Granted Patent B2
US 6,890,851 · App. 10/449,262 · Granted May 10, 2005

Interconnection structure and fabrication method thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,890,851
App. No.
10/449,262
Granted
May 10, 2005
Kind
B2
Abstract

An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k dielectric layer. The opening is then filled with a conductive material to form an interconnection structure. The stress redistribution layer has a heat expansion coefficient closer to that of the substrate, while such heat expansion coefficient differs more significantly from those of the first and second organic low-k material layers.

Claims (16)

1. An interconnection structure, comprising:

a first organic low-k material layer formed over a substrate;

a stress redistribution layer formed on the first organic low-k material layer, wherein the stress redistribution layer is selected from the group consisting of silicon carbide (SiC), silicon hydroxyl carbide (SiCOH), spin-on glass (SOG), hydrido organo siloxane polymer (HOSP) and a combination thereof;

a second organic low-k material layer formed on the stress redistribution layer; and

an interconnection formed in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k material layer.

2. The interconnection structure according to claim 1 , wherein the interconnection includes a via.

3. The interconnection structure according to claim 1 , wherein the interconnection includes a conductive line.

4. The interconnection structure according to claim 1 , wherein the interconnection includes a dual damascene comprising a via and a conductive line formed above the via.

5. The interconnection structure according to claim 4 , wherein the stress redistribution layer is formed in between a top portion and bottom portion of the via.

6. The interconnection structure according to claim 4 , wherein the stress redistribution layer is formed in between a top portion and bottom portion of the conductive line.

7. The interconnection structure according to claim 1 , wherein the first and second organic low-k material layers arc made of the same material.

8. The interconnection structure according to claim 1 , wherein the first and second organic low-k material layers are made of a material selected from a group consisting of polyimide, fluorinated polyimide, poly(arylene ether), parylene, polytetrafluoroethylene (PTFE), and beuzocyclobutene (BCB).

9. The interconnection structure according to claim 1 , further comprising a cap layer formed in between the first organic low-k material layer and the substrate.

10. The interconnection structure according to claim 9 , wherein the cap layer includes a silicon nitride layer.

11. The interconnection structure according to claim 1 , further comprising a diffusion barrier layer formed between the interconnection and device layers including the substrate, the first organic low-k material layer, the stress redistribution layer, and the second organic low-k material layer.

12. The interconnection structure according to claim 11 , wherein the diffusion barrier layer includes a titanium nitride layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →