Method and apparatus for enhancing the speed of a synchronous bus
View Patent ↗An apparatus for enhancing the speed of a synchronous bus includes a two register based FIFO with software control bits and a second clock signal. According to the invention, the second clock signal rd_clk is supplied by the same PLL that provides the main clock signal lg_clk. According to the invention, data is taken from the two registers in alternative clock cycles so that each of the register holds valid data for two clock cycles. A first software data bit is used to determine which of the two registers is unloaded first. Using the method and structure of the invention, the window for transferring valid data is increased and therefore the system employing the method and apparatus of the invention is more skew tolerant.
1. A synchronous bus system comprising:
a phase-locked loop (PLL);
a buffer element;
a Bus Application Specific Integrated Circuit (Bus ASIC), said Bus ASIC including a speed enhancement circuit;
said PLL being coupled to said speed enhancement circuit such that a first clock signal is provided to said speed enhancement circuit by said PLL;
said PLL being coupled to said speed enhancement circuit such that a second clock signal is provided to said speed enhancement circuit by said PLL;
said PLL being coupled to said buffer element such that said first clock signal is provided to said buffer element by said PLL; and
said buffer element being coupled to said speed enhancement circuit such that data is transferred between said buffer element and said speed enhancement circuit, wherein;
said data is held in said speed enhancement circuit for at least two cycles of said second clock signal.
2. The synchronous bus system of claim 1 , wherein; said speed enhancement circuit is a First-In/First-Out circuit (FIFO).
3. The synchronous bus system of claim 2 , wherein;
said FIFO comprises two registers, a first register and a second register.
4. The synchronous bus system of claim 3 , wherein;
said first clock signal is a signal lg_clk; and
said second clock signal is a signal rd_clk.
5. The synchronous bus system of claim 4 , wherein;
data is coupled to each of said first register and said second register of said FIFO and is held in each of said first register and said second register of said FIFO for two cycles of said signal rd_clk.
6. The synchronous bus system of claim 5 , wherein;
data is taken from one of said first register or said second register of said FIFO, alternatively, each cycle.
7. The synchronous bus system of claim 6 , wherein;
said speed enhancement circuit includes a software controlled bit for programmably determining whether data is taken first from said first register or first from said second register of said FIFO.
8. The synchronous bus system of claim 7 , wherein;
said buffer element is a fast-frame buffer.
9. The synchronous bus system of claim 8 , wherein;
said Bus ASIC is a Universal Port Architecture (UPA) Bus ASIC.
10. A synchronous bus system comprising:
a phase-locked loop (PLL);
a fast frame buffer;
a Bus Application Specific Integrated Circuit (Bus ASIC), said Bus ASIC including a speed enhancement circuit, said speed enhancement circuit comprising a First-In/First-Out circuit (FIFO), said FIFO comprising a first register and a second register;
said PLL being coupled to said speed enhancement circuit such that a first clock signal, lg_clk, is provided to said speed enhancement circuit by said PLL;
said PLL being coupled to said speed enhancement circuit such that a second clock signal, rd_clk, is provided to said speed enhancement circuit by said PLL;
said PLL being coupled to said fast-frame buffer such that said first clock signal is provided to said fast-frame buffer by said PLL; and
said fast-frame buffer being coupled to said speed enhancement circuit such that data is transferred between said fast-frame buffer and said speed enhancement circuit, wherein;
said data is coupled to each of said first register and said second register of said FIFO of said speed enhancement circuit and is held in each of said first register and said second register of said FIFO for two cycles of said signal rd_clk, further wherein;
said data is taken from one of said first register or said second register of said FIFO, alternatively, each cycle of said first clock signal.
11. The synchronous bus system of claim 10 , wherein;
said speed enhancement circuit includes a software controlled bit for programmably determining whether data is taken first from said first register or first from said second register of said FIFO.
12. The synchronous bus system of claim 11 , wherein;
said Bus ASIC is a Universal Port Architecture (UPA) Bus ASIC.
13. A synchronous bus system comprising:
a first clock signal;
a second clock signal;
a buffer element;
a Bus Application Specific Integrated Circuit (Bus ASIC), said Bus ASIC including a speed enhancement circuit;
said first clock signal being coupled to said speed enhancement circuit;
said second clock signal being coupled to said speed enhancement circuit;
said first clock signal being coupled to said buffer element; and
said buffer element being coupled to said speed enhancement circuit such that data is transferred between said buffer element and said speed enhancement circuit, wherein;
said data is held in said speed enhancement circuit for at least two cycles of said second clock signal.
14. A synchronous bus system comprising:
a first clock signal;
a second clock signal;
a fast frame buffer;
a Bus Application Specific Integrated Circuit (Bus ASIC), said Bus ASIC including a speed enhancement circuit, said speed enhancement circuit comprising a First-In/First-Out circuit (FIFO), said FIFO comprising a first register and a second register;
said first clock signal being coupled to said speed enhancement circuit;
said second clock signal being to coupled said speed enhancement;
said first clock signal being coupled to said fast-frame buffer; and
said fast-frame buffer being coupled to said speed enhancement circuit such that data is transferred between said fast-frame buffer and said speed enhancement circuit, wherein;
said data is coupled to each of said first register and said second register of said FIFO of said speed enhancement circuit and is held in each of said first register and said second register of said FIFO for two cycles of said second clock signal, further wherein;
said data is taken from one of said first register or said second register of said FIFO, alternatively, each cycle of said first clock signal.
15. A method for enhancing the speed of a synchronous bus system comprising:
providing a phase-locked loop (PLL);
providing a buffer element;
providing a Bus Application Specific Integrated Circuit (Bus ASIC), said Bus ASIC including a speed enhancement circuit;
coupling said PLL to said speed enhancement circuit such that a first clock signal is provided to said speed enhancement circuit by said PLL;
coupling said PLL to said speed enhancement circuit such that a second clock signal is provided to said speed enhancement circuit by said PLL;
coupling said PLL to said buffer element such that said first clock signal is provided to said buffer element by said PLL;
coupling said buffer element to said speed enhancement circuit such that data is transferred between said buffer element and said speed enhancement circuit; and
holding said data in said speed enhancement circuit for at least two cycles of said second clock signal.
16. The method for enhancing the speed of a synchronous bus system of claim 15 , wherein;
said speed enhancement circuit is a First-In/First-Out circuit (FIFO).
17. The method for enhancing the speed of a synchronous bus system of claim 16 , wherein;
said FIFO comprises two registers, a first register and a second register.
18. The method for enhancing the speed of a synchronous bus system of claim 17 , wherein;
said first clock signal is a signal lg_clk; and
said second clock signal is a signal rd_clk.
19. The method for enhancing the speed of a synchronous bus system of claim 18 , further comprising;
coupling data to each of said first register and said second register of said FIFO; and
holding said data in each of said first register and said second register of said FIFO for two cycles of said signal rd_clk.
20. The method for enhancing the speed of a synchronous bus system of claim 19 , further comprising;
taking data from one of said first register or said second register of said FIFO, alternatively, each cycle of said first clock signal, lg_clk.
21. The method for enhancing the speed of a synchronous bus system of claim 20 , wherein;
said speed enhancement circuit includes a software controlled bit for programmably determining whether data is taken first from said first register or first from said second register of said FIFO.
22. The method for enhancing the speed of a synchronous bus system of claim 21 , wherein;
said buffer element is a fast-frame buffer.
23. The method for enhancing the speed of a synchronous bus system of claim 22 , wherein;
said Bus ASIC is a Universal Port Architecture (UPA) Bus ASIC.
24. A method for enhancing the speed of a synchronous bus system comprising:
providing a phase-locked loop (PLL);
providing a fast frame buffer;
providing a Bus Application Specific Integrated Circuit (Bus ASIC), said Bus ASIC including a speed enhancement circuit, said speed enhancement circuit comprising a First-In/First-Out circuit (FIFO), said FIFO comprising a first register and a second register;
coupling said PLL to said speed enhancement circuit such that a first clock signal, lg_clk, is provided to said speed enhancement circuit by said PLL;
coupling said PLL to said speed enhancement circuit such that a second clock signal, rd_clk, is provided to said speed enhancement circuit by said PLL;
coupling said PLL to said fast-frame buffer such that said first clock signal is provided to said fast-frame buffer by said PLL;
coupling fast-frame buffer to said speed enhancement circuit such that data is transferred between said fast-frame buffer and said speed enhancement circuit;
coupling said data to each of said first register and said second register of said FIFO of said speed enhancement circuit;
holding said data in each of said first register and said second register of said FIFO for two cycles of said signal rd_clk; and
taking said data from one of said first register or said second register of said FIFO, alternatively, each cycle of said first clock signal.
25. The method for enhancing the speed of a synchronous bus system of claim 24 , wherein;
said speed enhancement circuit includes a software controlled bit for programmably determining whether data is taken first from said first register or first from said second register of said FIFO.
26. The method for enhancing the speed of a synchronous bus system of claim 25 , wherein;
said Bus ASIC is a Universal Port Architecture (UPA) Bus ASIC.
27. A method for enhancing the speed of a synchronous bus system comprising:
providing a first clock signal;
providing a second clock signal;
providing a buffer element;
providing a Bus Application Specific Integrated Circuit (Bus ASIC), said Bus ASIC including a speed enhancement circuit;
coupling said first clock signal to said speed enhancement circuit;
coupling said second clock signal to said speed enhancement circuit;
coupling said first clock signal to said buffer element;
coupling said buffer element to said speed enhancement circuit such that data is transferred between said buffer element and said speed enhancement circuit; and
holding said data in said speed enhancement circuit for at least two cycles of said second clock signal.
28. A method for enhancing the speed of a synchronous bus system comprising:
providing a first clock signal;
providing a second clock signal;
providing a fast frame buffer;
providing a Bus Application Specific Integrated Circuit (Bus ASIC), said Bus ASIC including a speed enhancement circuit, said speed enhancement circuit comprising a First-In/First-Out circuit (FIFO), said FIFO comprising a first register and a second register;
coupling said first clock signal to said speed enhancement circuit;
coupling said second clock signal to said speed enhancement circuit;
coupling said first clock signal to said fast-frame buffer;
coupling said fast-frame buffer to said speed enhancement circuit such that data is transferred between said fast-frame buffer and said speed enhancement circuit;
coupling said data to each of said first register and said second register of said FIFO of said speed enhancement circuit;
holding said data in each of said first register and said second register of said FIFO for two cycles of said second clock signal; and taking said data from one of said first register or said second register of said FIFO, alternatively, each cycle of said first clock signal.