Systems and methods using non-volatile memory cells

1. A non-volatile memory system, comprising:

a transistor having a source and a drain, the transistor formed from a short-range atomic order substrate, the source and drain configured to alternately receive a first bias voltage creating a potential difference between the source and the drain;

a dielectric for storing charge; and

a non-floating gate positioned adjacent to the dielectric and configured to receive a threshold bias voltage to enable movement of the charge between the source and the drain and the dielectric, wherein the transistor, the dielectric, and the non-floating gate comprise a first row, and further comprising a second row positioned adjacent to the first row, the second row comprising a second transistor that includes a second source and a second drain, the second transistor formed from a second short-range atomic order substrate, a second dielectric for storing charge, a second non-floating gate on the second dielectric for receiving a threshold bias voltage to enable movement of the charge between the second source and the second drain and the second dielectric, wherein the second source and the second drain of the second row are separated from the non-floating sate of the first row by an isolation layer.

2. The non-volatile memory system of claim 1 , wherein the charge movement into the dielectric occurs by direct tunneling upon the threshold bias voltage substantially achieving a threshold voltage of the transistor and the first bias voltage creating a potential difference between the source and the drain, wherein erasure of the charge in the dielectric occurs by applying the threshold bias voltage to the non-floating gate, the threshold bias voltage having a reverse polarity and of a substantially similar magnitude.

3. The non-volatile memory system of claim 1 , further comprising an interface dielectric and an integrated circuit device, wherein the interface dielectric is electrically coupled to the first row and the second row, wherein the integrated circuit device is electrically coupled to the interface dielectric, wherein said integrated circuit device is a semiconductor device that includes a driver and accessing circuitry for accessing a charge value from the dielectric of the first row and the second dielectric of the second row.

4. A non-volatile memory cell, comprising:

a short-range atomic order substrate having a transistor;

a non-floating gate;

a dielectric located between the short-range atomic order substrate and the non-floating gate; and

an intrinsic current layer that facilitates charge movement between the short-range atomic order substrate and the dielectric, wherein the dielectric stores charge and the transistor comprises a first reaction at a first potential and a second region at a second potential.

5. The non-volatile memory cell of claim 4 , wherein the dielectric, responsive to a threshold bias voltage applied to the non-floating gate, receives charge in proximity to at least one of the first region and the second region.

6. A non-volatile memory system, comprising:

a first row comprising a first transistor, a first dielectric, and a first non-floating gate, the first transistor formed from a first substrate having a short-range atomic order and configured to create a potential difference between a first source and a first drain, the first dielectric configured to store an electrical charge, the first non-floating gate positioned adjacent to the first dielectric and configured to receive a first threshold bias voltage to enable movement of the charge between the first-source and the first drain and the first dielectric;

an isolation layer juxtaposed to the first row; and

a second row juxtaposed to the isolation layer, the second row comprising a second transistor, a second dielectric, and a second non-floating gate, the second transistor formed from a second substrate having a short-range atomic order and configured to create a potential difference between a second source and a second drain, the second dielectric configured to store an electrical charge, the second non-floating gate adjacent to the second dielectric and configured to receive a second threshold bias voltage to enable movement of the charge between the second source and the second drain and the second dielectric.

7. The non-volatile memory system of claim 6 , further comprising an interface dielectric coupled to the first row and the second row.

8. The non-volatile memory device of claim 7 , further comprising an integrated circuit device coupled to the interface dielectric.

9. The non-volatile memory device of claim 8 , wherein said integrated circuit device is a semiconductor device that includes a driver and accessing circuitry for selectively accessing a charge value from each of the first dielectric and the second dielectric.

10. A non-volatile memory cell, comprising:

a substrate having short-range atomic order;

a non-floating gate located within the substrate;

a first dielectric layer juxtaposed with the substrate and configured to store an electrical charge; and

an intrinsic current layer interposed between the first dielectric layer and a second dielectric layer, the second dielectric layer having inserted therein a first region at a first potential and a second region at a second potential, wherein the intrinsic current layer facilitates charge movement between at least one of the first and second regions and the substrate.

11. The non-volatile memory cell of claim 10 , wherein the first dielectric, responsive to a threshold bias voltage applied to the non-floating gate, receives charge in proximity to at least one of the first region and the second region.

12. The non-volatile memory cell of claim 10 , further comprising an interface dielectric layer juxtaposed with the substrate.

13. The non-volatile memory cell of claim 12 , wherein the interface dielectric layer couples the memory cell to a semiconductor device.

14. The non-volatile memory cell of claim 10 , further comprising an isolation layer juxtaposed with the second dielectric layer.

15. A non-volatile memory cell, comprising:

a semiconductor layer having short-range atomic order substantially encompassing a first region at a first potential and a second region at a second potential, the first region separated from the second region by a portion of the semiconductor layer;

a dielectric layer juxtaposed with the substrate and configured to store an electrical charge; and

a non-floating gate juxtaposed with the dielectric layer and opposed to the first and second regions.

16. The non-volatile memory cell of claim 15 , wherein the dielectric layer, responsive to a threshold bias voltage applied to the non-floating gate, receives charge in proximity to at least one of the first region and the second region.

17. The non-volatile memory cell of claim 15 , further comprising an interface dielectric layer juxtaposed with the semiconductor layer.

18. The non-volatile memory cell of claim 17 , wherein the interface dielectric layer couples the memory cell to a semiconductor device.

19. The non-volatile memory cell of claim 15 , further comprising an isolation layer juxtaposed with the dielectric layer.

20. The non-volatile memory system of claim 1 , further comprising an interface dielectric coupled to the first row and the second row.

21. The non-volatile memory device of claim 20 , further comprising an integrated circuit device coupled to the interface dielectric.

22. The non-volatile memory device of claim 21 , wherein said integrated circuit device is a semiconductor device that includes a driver and accessing circuitry for selectively accessing a charge value from each of the first dielectric and the second dielectric.

23. The non-volatile memory cell of claim 4 , wherein the dielectric layer, responsive to a threshold bias voltage applied to the non-floating gate, receives charge in proximity to at least one of the first region and the second region.

24. The non-volatile memory cell of claim 4 , further comprising an interface dielectric layer juxtaposed with the semiconductor layer.

25. The non-volatile memory cell of claim 24 , wherein the interface dielectric layer couples the memory cell to a semiconductor device.

26. The non-volatile memory cell of claim 4 , further comprising an isolation layer juxtaposed with the dielectric layer.