Patent Assignment
Reel/Frame 026008/0690
Assignment of Assignor's Interest
Recorded: 2011-03-11
Pages: 12
Assignors
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Executed: 2010-06-25
HEWLETT-PACKARD COMPANY
Executed: 2010-06-25
Assignee
SAMSUNG ELECTRONICS CO., LTD.
416, MAETAN-DONG, YEONGTONG-GU, SUWON-SI, GYEONGGI-DO, KOREA, REPUBLIC OF
Covered Properties
(178)
Semiconductor Package Having Wraparound Metallization
Patent:
5,235,211 →
Application:
07/542,179 →
Method and Apparatus for Reducing Buffer Storage in a Read-Modify- Write Operation
Patent:
5,235,693 →
Application:
07/582,475 →
Gentle Package Extraction Tool and Method
Patent:
5,224,263 →
Application:
07/722,656 →
Sequential Parity Correction for Error-Correcting Ram Array
Patent:
5,515,381 →
Application:
07/823,078 →
Data Integrity Assurance in a Disk Drive Upon a Power Failure
Patent:
5,359,728 →
Application:
07/866,377 →
Method and Apparatus for Imaging and Analysis of Corneal Tissue
Patent:
5,404,884 →
Application:
07/931,271 →
Cache System for Reducing Memory Latency Times
Patent:
5,404,484 →
Application:
07/945,561 →
Hollow Chip Package and Method of Manufacture
Patent:
5,885,853 →
Application:
07/979,552 →
Method and Apparatus for Parity Generation
Patent:
5,557,622 →
Application:
08/000,518 →
Network Connection Scheme
Patent:
5,729,752 →
Application:
08/019,499 →
Burst Srams for Use with a High Speed Clock
Patent:
5,604,884 →
Application:
08/034,288 →
Circuit for Disabling an Address Masking Control Signal Using or Gate When a Microprocessor Is in a System Management Mode
Patent:
5,509,139 →
Application:
08/034,300 →
Interleaving Read and Write Operations on a Bus and Minimizing Buffering on a Memory Module in a Computer System
Patent:
6,807,609 →
Application:
08/067,262 →
A Method for Providing a Memory Medel of a Memory Device for Use in Simulation
Patent:
6,144,930 →
Application:
08/073,911 →
Programmable Error-Checking Matrix for Digital Communication System
Patent:
5,396,505 →
Application:
08/087,545 →
An Ic Which Can Be Used as a Programmable Logic Cell Array or as a Register File
Patent:
5,315,178 →
Application:
08/113,578 →
Least Recently Used Replacement Apparatus for a System with a Set Associative Cache
Patent:
5,325,511 →
Application:
08/121,978 →
Electrical Interconnect for a Head/Arm Assembly of Computer Disk Drives
Patent:
5,422,764 →
Application:
08/138,292 →
Method for Addressing a Block Addresasble Memory Using a Gray Code
Patent:
5,535,354 →
Application:
08/200,931 →
Memory Processor That Prevents Errors When Load Instructions Are Moved in the Execution Sequence
Patent:
5,475,823 →
Application:
08/261,647 →
System for Handling Cache Memory Victim Data Which Transfers Data from Cache to the Interface While Cpu Performs a Cache Lookup Using Cache Status Information
Patent:
5,537,575 →
Application:
08/268,403 →
Method and Apparatus for Adaptive Memory Access
Patent:
5,566,325 →
Application:
08/269,259 →
Paddleless Molded Plastic Semiconductor Chip Package
Patent:
5,604,376 →
Application:
08/269,294 →
System Independent Interface for Performance Counters
Patent:
5,537,541 →
Application:
08/291,240 →
Scalable Register File Organization for a Computer Architecture Having Multiple Functional Units or a Large Register File
Patent:
5,513,363 →
Application:
08/293,862 →
Apparatus and Method for Reducing Delays Due to Branches
Patent:
5,664,135 →
Application:
08/313,980 →
Method and System for Deferring Exceptions Generated During Speculative Execution
Patent:
5,692,169 →
Application:
08/324,940 →
Mirrored Memory Multi-Processor System
Patent:
5,495,570 →
Application:
08/329,326 →
Using an Address Pin as a Snoop Invalidate Signal During Snoop Cycles
Patent:
5,617,557 →
Application:
08/339,086 →
Apparatus for Caching Smram in an Intel Processor Based Computer System Employing System Management Mode
Patent:
5,544,344 →
Application:
08/349,853 →
Method of Determining the Configuration of Devices Installed on a Computer Bus
Patent:
5,628,027 →
Application:
08/367,453 →
Independently Mounted Cooling Fins for a Low-Stress Semiconductor Package
Patent:
6,208,513 →
Application:
08/373,718 →
Computer System and Method for Evaluating Predicates and Boolean Expressions
Patent:
6,023,751 →
Application:
08/400,414 →
Zone Bit Recording Enhanced Video Data Layout
Patent:
5,774,714 →
Application:
08/411,364 →
Tileable Gate Array Cell for Programmable Logic Devices and Gate Array Having Tiled Gate Array Cells
Patent:
5,519,629 →
Application:
08/432,234 →
Graph Partitioning Engine Based on Programmable Gate Arrays
Patent:
5,761,077 →
Application:
08/447,469 →
Circuit for Disabling an Address Masking Control Signal When a Microprocessor Is in a System Management Mode
Patent:
5,664,225 →
Application:
08/524,799 →
Multi-Ported Data Storage Device with Improved Cell Stability
Patent:
5,590,087 →
Application:
08/533,133 →
Apparatus for Providing Improved Memory Access Periods in Page Mode Cache Systems with Pipelined Cache Access and Main Memory Address Replay
Patent:
5,553,270 →
Application:
08/562,713 →
Improved Computer Architecture for Reducing Delay Due to Branch Instructions
Patent:
5,615,386 →
Application:
08/588,151 →
Method and System for Propagating Exception Status in Data Register and for Detecting Exceptions Form Speculative Operations with Non-Speculative Operations
Patent:
5,778,219 →
Application:
08/597,784 →
Circuit for Testing Microprocessor Memories
Patent:
5,621,883 →
Application:
08/613,597 →
Apparatus and Method for Configuring a Reconfigurable Electronic System Having Defective Resources
Patent:
5,790,771 →
Application:
08/641,467 →
Circuit for Correcting Cache Incoherency Problems
Patent:
5,692,154 →
Application:
08/645,921 →
Using an Address Pin as a Snoop Invalidate Signal During Snoop Cycles
Patent:
5,724,550 →
Application:
08/658,004 →
Data Handling System with Circular Queue Formed in Paged Memory
Patent:
5,873,089 →
Application:
08/689,893 →
Scaled Memory Allocation System
Patent:
6,131,150 →
Application:
08/692,649 →
A Method for Refreshing a Memory, Controlled by a Memory Controller in a Computer System, in a Self-Refresh Mode While Scanning the Memory Controller
Patent:
5,754,557 →
Application:
08/720,960 →
Paddleless Molded Plastic Semiconductor Chip Package
Patent:
5,776,800 →
Application:
08/730,536 →
Controlling Sdram Memory by Using Trauncated Burst Read-Modify-Write Memory Operations
Patent:
5,974,514 →
Application:
08/747,320 →
Method and Apparatus for Detecting Memory Device Types
Patent:
5,974,501 →
Application:
08/770,611 →
Computer System with System Rom Including Serial-Access Prom Coupled to an Auto-Configuring Memory Controller and Method of Shadowing Bios Code from Prom
Patent:
5,951,685 →
Application:
08/771,557 →
Method and Apparatus for Using Extended Data Output Memory Devices in a System Designed for Fast Page Mode Memory Devices
Patent:
6,034,919 →
Application:
08/775,315 →
Burst Srams for Use with a High Speed Clock
Patent:
5,809,549 →
Application:
08/801,738 →
Instruction Unit Having a Partitioned Cache
Patent:
5,933,850 →
Application:
08/843,795 →
Accessing Multiple Independent Microkernels Existing in a Globally Shared Memory System
Patent:
5,933,857 →
Application:
08/845,306 →
Microprocessor Chip Having a Memory That Is Reconfigurable to Function as on-Chip Main Memory or an on-Chip Cache
Patent:
6,678,790 →
Application:
08/871,295 →
Circuit for Disabling an Address Masking Control Signal When a Microprocessor Is in a System Management Mode
Patent:
5,857,116 →
Application:
08/918,838 →
Match and Match Address Signal Prioritization in a Content Addressable Memory Encoder
Patent:
6,069,573 →
Application:
08/920,665 →
Memory Error Containment in Network Cache Environment
Patent:
6,081,876 →
Application:
08/935,242 →
Main Memory Bank Indexing Scheme That Optimizes Consecutive Page Hits by Linking Main Memory Bank Address Organization to Cache Memory Address Organization
Patent:
6,070,227 →
Application:
08/963,673 →
Method of Management of a Circular Queue for Asynchronous Access
Patent:
6,145,061 →
Application:
09/003,201 →
Determining Thresholds and Wrap-Around Conditions in a First-in-First-Out Memory Supporting a Variety of Read and Write Transaction Sizes
Patent:
6,134,629 →
Application:
09/015,415 →
Integrated Hierarchical Memory Overlay Method for Improved Processor Performance
Patent:
6,209,061 →
Application:
09/032,969 →
Method and Apparatus for Resetting a Random Access Memory
Patent:
6,192,447 →
Application:
09/058,001 →
Catheter Cot
Patent:
5,980,507 →
Application:
09/070,118 →
Method and Apparatus for a Low Power Self Test of a Memory Subsystem
Patent:
6,067,649 →
Application:
09/095,435 →
Method of Determining Signal Delay of a Resource in a Reconfigurable System Having Multiple Resources
Patent:
6,298,453 →
Application:
09/098,578 →
Sharing a Single Serial Port Between System Remote Access Software and a Remote Management Microcontroller
Patent:
6,192,423 →
Application:
09/131,650 →
Methods and Apparatus for Processing Load Instructions in the Presence of Ram Array and Data Bus Conflicts
Patent:
6,374,344 →
Application:
09/200,248 →
System and Method for Multiplication Modulo (2N + 1)
Patent:
6,321,247 →
Application:
09/222,254 →
Method and Apparatus to Share Instruction Images in a Virtual Cache
Patent:
6,298,411 →
Application:
09/225,775 →
System and Method for Managing Data in an Asynchronous I/O Cache Memory to Maintain a Predetermined Amount of Storage Space That Is Readily Availble
Patent:
6,295,582 →
Application:
09/232,194 →
Apparatus and Method for Enhancing Data Transfer to or from a Sdram System
Patent:
6,226,755 →
Application:
09/236,871 →
Computer System with System Rom Including Serial-Access Prom Coupled to an Auto-Configuring Memory Controller and Method of Shadowing Bios Code from Prom
Patent:
6,112,303 →
Application:
09/252,431 →
Preemptive Replacement Strategy for a Caching Dynamic Translator
Patent:
6,237,065 →
Application:
09/312,300 →
Mechanism for Detecting Continuity Modules in a Direct Rambus Dram Subsystem
Patent:
6,636,943 →
Application:
09/364,716 →
Programmatic Iteration Scheduling for Parallel Processors
Patent:
6,438,747 →
Application:
09/378,393 →
Cache Bank Conflict Avoidance and Cache Collision Avoidance
Patent:
6,446,157 →
Application:
09/399,010 →
Redundancy programming using addressable scan paths to reduce the number of required fuses
Patent:
6,249,465 →
Application:
09/506,620 →
Collapsible Hub Assembly
Patent:
6,508,433 →
Application:
09/603,250 →
Enhanced Clock Forwarding Data Recovery
Patent:
6,977,979 →
Application:
09/652,459 →
Checkpoint Computer System Utilizing a Fifo Buffer to Re-Scynchronize and Recover the System on the Detection of an Error
Patent:
6,810,489 →
Application:
09/656,551 →
Apparatus and Method for Detecting and Storing Information Relating to an Animal
Patent:
6,402,692 →
Application:
09/666,005 →
Portable Scanning Apparatus Having High Storage Capacity
Patent:
6,775,034 →
Application:
09/689,201 →
System and Method for Detecting Attempts to Access Data Residing Outside of Allocated Memory
Patent:
6,697,971 →
Application:
09/695,363 →
Content addressable memory cell with a bootstrap improved compare
Patent:
6,301,140 →
Application:
09/697,746 →
Resource Access/Return System
Patent:
6,873,840 →
Application:
09/710,128 →
Data recording methodology and methods for facilitating data recovery with emitter failure
Patent:
6,275,410 →
Application:
09/710,356 →
Afm Version of Diode- and Cathodoconductivity - and Cathodoluminescence-Based Data Storage Media
System and method for utilizing checksums to recover data
Patent:
6,317,857 →
Application:
09/759,853 →
Cache Test Sequence for Single-Ported Row Repair Cam
Electron Source Having Planar Emission Region and Focusing Structure
Memory Manager for a Common Memory
Using Task Description Blocks to Maintain Information Regarding Operations
Storage System for Use in Custom Loop Accelerators and the Like
System and Method for Setting New Values for Configuration Parameters on a Device
Retiring Early-Completion Instruction to Improve Computer Operation Throughput
Data Storage Device
System and Method for Performing Backward Error Recovery in a Computer
Device Isolation Process Flow for Ars System
Method of Memory Management in a Multi-Threaded Environment and Program Storage Device
Relocation Table for Use in Memory Management
Pulse Train Writing of Worm Storage Device
Patent:
6,434,048 →
Application:
09/908,901 →
Fault-Tolerant Solid State Memory
Preventing Floppy Disk Data Corruption
Write Pulse Limiting for Worm Storage Device
Patent:
6,434,060 →
Application:
09/917,882 →
Method and Apparatus for Performing Integer Multiply Operations Using Primitive Multi-Media Operations That Operate on Smaller Operands
One-Time Programmable Unit Memory Cell Based on Vertically Oriented Fuse and Diode and One-Time Programmable Memory Using the Same
Apparatus and Method for Automatically Disabling Cell Phone Ringing
Thin Film Transistor Memory Device
Passive Release Avoidance Technique
Dimm Connector Accomodating Sideband Signals for Battery Status and/or Control
Device for Automatically Translating and Presenting Voice Messages as Text Messages
Method for Verifying Abstract Memory Models of Shared Memory Multiprocessors
Diode-Based Multiplexer
Systems and Methods for Controlling Communication with Nonvolatile Memory Devices
Processor Multiple Function Units Executing Cycle Specifying Variable Length Instruction Block and Using Common Target Block Address Updated Pointers
Low Latency Lock for Multiprocessor Computer System
Block Data Mover Adapted to Contain Faults in a Partitioned Multiprocessor System
Pausing a Transfer of Data
Automated Multiple Data Unit Transfers Between a Host Device and a Storage Medium
Buffer Management for Data Transfers Between a Host Device and a Storage Medium
Exchanging Operation Parameters Between a Data Storage Device and a Controller
High Density Data Storage Module
Memory Image Verification System and Method
Atomic Resolution Storage Device
Armored Peripheral Case
Microprocessor Cache Design Initialization
Method and Apparatus for Recovering from Corrupted System Firmware in a Computer System
System and Method for an Enhanced Analog Video Interface
Direct Connect Solid-State Storage Device
Patent:
6,665,201 →
Application:
10/202,051 →
Branch Reconfigurable Systems and Methods
System and Method for Independent Branching in Systems with Plural Processing Elements
Method and System for Memory Management Optimization
Luminescence-Phase Change Based Data Storage
Channeled Dielectric Re-Recordable Data Storage Medium
Linked-List Early Race Resolution Mechanism
System and Method Enabling Efficient Cache Line Reuse in a Computer System
Retry-Based Late Race Resolution Mechanism for a Computer System
Channel-Based Late Race Resolution Mechanism for a Computer System
Device Isolation Process Flow for Ars System
System and Method for Transferring Data Through a Video Interface
Pipeline Stage Initialization via Task Frame Accessed by a Memory Pointer Propagated Among the Pipeline Stages
System for and Method of Operating a Cache
Memory Having Multiple Write Ports and Write Insert Unit, and Method of Operation
Unbalanced Inclusive Tags
Method for Precharging Word and Bit Lines for Selecting Memory Cells Within a Memory Array
Memory Array
Device Identification Using a Memory Profile
Providing an Arrangement of Memory Devices to Enable High-Speed Data Access
Systems and Methods Using Non-Volatile Memory Cells
Methods and Apparatuses for Determining the State of a Memory Element
Multiple Buffer Memory Interface
System and Method for Erasing High-Density Non-Volatile Fast Memory
System and Method for Analysis of Cache Array Test Data
Systems and Methods for Storing Data on Computer Systems
Data Storage Device
Defective Data Site Information Storage
Spare Data Site Allocation
System Having a Storage Controller That Modifies Operation of a Storage System Based on the Status of a Data Transfer
Organizing Data Objects in a Storage Device
Storage Device Having a Resistance Measurement System
System for Error Correction Coding and Decoding
Data Processing System and Method
Memory Manager for a Common Memory
Semiconductor Storage Device
Focusing Structure for Electron Source
Method and Apparatus for the Separation and Collection of Particles
Thin Film Transistor Memory Device
Device Identification Using a Memory Profile
System and Method for Writing Data Using an Electron Beam
Test Subject Monitoring Device
Patent:
7,386,333 →
Application:
11/117,974 →
Self-Timed Memory Device Providing Adequate Charging Time for Selected Heaviest Loading Row
Performing Read-Ahead Operation for a Direct Input/Output Request
Fingerprint Capture
Electron Tube Amplification
Patent:
7,454,221 →
Application:
11/179,260 →
Method and Apparatus for Variable-Resolution Memory
Related Assignments
(1)
Other recorded transfers of the patents in this record — the chain of ownership.