IP Library Granted Patent US 6,950,912
Granted Patent B2
US 6,950,912 · App. 10/870,847 · Granted Sep 27, 2005

Memory manager for a common memory

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Quick Facts
Patent No.
US 6,950,912
App. No.
10/870,847
Granted
Sep 27, 2005
Kind
B2
Abstract

The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Claims (14)

1. A hardware-based memory management system for use with a common primary memory shared by multiple entities, wherein each entity is configured to request access to the common primary memory, the system comprising:

at least two request queues, each queue being configured to receive requests from the multiple entities for access to the primary-common memory and to hold such requests, wherein a first queue is configured to hold requests having a higher priority than that of requests in a second queue;

a prioritizer configured to determine a priority of requests and direct a request into one of the queues based upon the determined priority of the request, wherein the prioritizer directs requests into the first queue that generally are performed faster than requests directed into the second queue;

a queue-to-memory handler configured to provide primary-common memory access to requests in the queues, wherein requests in the first queue are provided access before requests in the second queue.

2. A hardware-based memory management system for use with a common primary memory shared by multiple entities, wherein each entity is configured to request access to the common primary memory, the system comprising:

at least two request queues, each queue being configured to receive requests from the multiple entities for access to the primary-common memory and to hold such requests, wherein a first queue is configured to hold requests having a higher priority than that of requests in a second queue;

a prioritizer configured to determine a priority of requests and direct a request into one of the queues based upon the determined priority of the request, wherein the prioritizer is further configured to determine a priority of requests within one of the queues, thereby reordering the requests in one of the queues;

a queue-to-memory handler configured to provide primary-common memory access to requests in the queues, wherein requests in the first queue are provided access before requests in the second queue.

3. A hardware-based memory management system for use with a common primary memory shared by multiple entities, wherein each entity is configured to request access to the common primary memory, the system comprising;

at least two request queues, each queue being configured to receive requests from the multiple entities for access to the primary-common memory and to hold such requests, wherein a first queue is configured to hold requests having a higher priority than that of requests in a second queue;

a prioritizer configured to determine a priority of requests and direct a request into one of the queues based upon the determined priority of the request;

a queue-to-memory handler configured to provide primary-common memory access to requests in the queues, wherein requests in the first queue are provided access before requests in the second queue, the handler being further configured to:

provide primary-common memory access to all of the requests in the first queue before providing access to requests in the second queue;

pre-empt a current primary-common memory access resulting from a request from the second queue to provide memory access to a newly arrived request in the first queue.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2011
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.; HEWLETT-PACKARD COMPANY
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 026008/0690 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2010
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.; HEWLETT-PACKARD COMPANY
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 025443/0543 →