Semiconductor device
A semiconductor device having an accumulation channel SiC-MISFET structure includes a p-type SiC layer 10 formed on an SiC substrate, an n-type channel layer 20, a gate insulating film 11, a gate electrode 12, and n-type source and drain layers 13 a and 13 b . The channel layer 20 includes an undoped layer 22 and a δ doped layer 21 which is formed in the vicinity of the lower end of the undoped layer 22. Since the channel layer 20 includes the high-concentration δ doped layer 21 in its deeper portion, the electric field in the surface region of the channel layer is weakened, thereby allowing the current driving force to increase.
1. A semiconductor device comprising:
a semiconductor substrate;
a semiconductor region of a first conductivity type formed in at least a part of the semiconductor substrate;
a modulation-doped channel layer formed on the first-conductivity-type semiconductor region, having a non-uniform impurity concentration distribution, and being of a second conductivity type;
a gate insulating film formed on the channel layer;
a gate electrode formed on the gate insulating film; and
a source layer of the second conductivity type formed in the first-conductivity-type semiconductor region so as to be located laterally with respect to the gate electrode,
wherein given that y is depth into the channel layer from the surface thereof; N(y), a function of the depth y, is the impurity concentration of the channel layer in the depth direction; N cm is the average impurity concentration of the channel layer; and yc, which is the depth of the center of gravity of the impurity concentration distribution in the depth direction in the channel layer, is given by the following equation:
yc=|{∫N ( y )· y·dy}/N cm |, then
the channel layer is configured to satisfy the following equation:
yc≧T ch /2
where T ch is the thickness of the entire channel layer.
2. The semiconductor device of claim 1 , characterized in that the semiconductor substrate is an SiC substrate.
3. The semiconductor device of claim 1 , characterized in that the channel layer is configured to be pinched off by a depletion layer that extends from the gate insulating film and a depletion layer that extends from the first-conductivity-type semiconductor region when the potential of the gate electrode is about 0 V.
4. The semiconductor device of claim 3 , characterized in that the thickness T ch of the channel layer satisfies the following equation:
T
ch
≦
[
(
2
ɛ
s
/
q
)
{
(
N
c
m
+
N
bs
)
/
(
N
c
m
·
N
bs
)
}
·
V
bl
}
]
+
[
(
2
ɛ
s
/
q
)
(
1
/
(
N
c
m
)
{
ϕ
m
s
-
(
Q
/
C
ox
)
}
]
where |N bs | is the absolute value of first-conductivity-type impurity concentration of the first-conductivity-type semiconductor region; |N cm | is the absolute value of the average impurity concentration of the channel layer; ∈s is the vacuum dielectric constant; q is the elementary charge; φ ms is the surface potential of the channel layer; Q is electric charge in the gate insulating film; C ox is the capacitance of the gate insulating film; and V bl is difference in internal potential between the channel layer and the first-conductivity-type semiconductor layer.
5. The semiconductor device of claim 4 , characterized in that the absolute value |N bs | of the first-conductivity-type impurity concentration of the first-conductivity-type semiconductor region is higher than the absolute value |N cm | of the average second-conductivity-type impurity concentration of the channel layer.
6. The semiconductor device of claim 4 or 5 , characterized in that the channel layer includes a high-concentration doped layer and a low-concentration doped layer, wherein the high-concentration doped layer contains an impurity of the second conductivity type, and the low-concentration doped layer is of the second conductivity type and has an impurity concentration not more than one-tenth of the peak concentration of the high-concentration doped layer.
7. The semiconductor device of claim 6 , characterized in that the high-concentration doped layer is a δ doped layer formed below a mid-position of the channel layer.
8. The semiconductor device of claim 7 , characterized in that the thickness of the δ doped layer is not more than 10 nm.
9. The semiconductor device of claim 7 , characterized in that the first-conductivity-type impurity concentration of the first-conductivity-type semiconductor region is high to a degree at which the δ doped layer is depleted to a foot area of its concentration profile which has a low impurity concentration and is located alongside the gate electrode.
10. The semiconductor device of claim 7 , characterized in that the distance from an edge of the δ doped layer, which is located alongside the first-conductivity-type semiconductor region, to the first-conductivity-type semiconductor region is 20 nm or less.
11. The semiconductor device of claim 7 , characterized in that when a voltage of about 0 V is applied to the gate electrode, the depletion layer that extends from the gate electrode side and the depletion layer that extends from the first-conductivity-type semiconductor region make contact with each other in a foot area of a concentration profile for the δ doped layer, such that pinch-off is caused in the channel layer, the foot area having a low impurity concentration and located alongside the gate electrode.
12. The semiconductor device of claim 11 , characterized in that the impurity concentration of the foot area, being the pinch-off point, is not less than the impurity concentration of the low-concentration doped layer and not more than the peak concentration of the δ doped layer.
13. The semiconductor device of claim 11 , characterized in that when a voltage from about 0 V going to where the channel goes on is applied to the gate electrode, opening of the channel takes place in such a manner that the depletion layer that extends from the first-conductivity-type semiconductor region begins to expand from the foot area, being the pinch-off point, of the δ doped layer so as to extend to the interface between the channel layer and the gate insulating film.
14. The semiconductor device of claim 6 , characterized in that the high-concentration doped layer is a deep-portion δ doped layer formed below a mid-position of the channel layer, and
the semiconductor device further includes a surface-portion δ doped layer formed above the mid-portion of the channel layer.
15. The semiconductor device of claim 14 , characterized in that the impurity concentration of the surface-portion δ doped layer is lower than that of the deep-portion δ doped layer.
16. The semiconductor device of claim 6 , characterized in that the high-concentration doped layer is a graded doped layer in which impurity concentration decreases going from its lower part to its upper part.
17. The semiconductor device of claim 16 , characterized in that when a voltage of about 0 V is applied to the gate electrode, the depletion layer that extends from the gate electrode side and the depletion layer that extends from the first-conductivity-type semiconductor region make contact with each other in a graded region of an impurity concentration profile for the graded doped layer, such that pinch-off is caused in the channel layer.
18. The semiconductor device of claim 6 , characterized in that the high-concentration doped layer is a uniformly doped layer that is formed in contact with the first-conductivity-type semiconductor region and has a substantially uniform impurity concentration.
19. The semiconductor device of claim 18 , characterized in that the uniformly doped layer stops the depletion layer that extends from the first-conductivity-type semiconductor region so that the pinch-off point is stabilized in a substantially constant location.
20. The semiconductor device of claim 19 , characterized in that the impurity concentration of the uniformly doped layer is not less than that of the first-conductivity-type semiconductor region.
21. The semiconductor device of claim 19 , characterized in that where N s is the impurity concentration of the uniformly doped layer, the thickness T ds of the uniformly doped layer satisfies the following equation:
T
ds
≧
{
N
bs
/
(
N
s
+
N
bs
)
}
×
[
(
2
ɛ
s
/
q
)
·
{
(
N
s
+
N
bs
)
/
(
N
s
·
N
bs
)
}
·
V
bl
]
.
22. The semiconductor device of claim 19 , characterized in that where N ud is the impurity concentration of the low-concentration doped layer in the channel layer, the thickness T ud of the low-concentration doped layer satisfies the following equation:
T ud ≦√[(2 ∈s/q )(1 /N ud ){φ ms −( Q/C ox )}]).
23. The semiconductor device of claim 22 , characterized in that the thickness T ud +T ds of the entire channel layer satisfies the following equation:
T
ud
+
T
ds
≦
[
(
2
ɛ
s
/
q
)
·
{
(
N
s
+
N
bs
)
/
(
N
s
·
N
bs
)
}
·
V
bl
]
+
[
(
2
ɛ
s
/
q
)
(
1
/
(
N
ud
)
{
ϕ
m
s
-
(
Q
/
C
ox
)
}
]
.
24. The semiconductor device of any one of claims 19 through 23 , characterized in that when a voltage of about 0 is applied to the gate electrode, the depletion layer that extends from the gate insulating film side and the depletion layer that extends from the first-conductivity-type semiconductor region side come into contact with each other and cause pinch-off in an impurity-concentration-profile region of transition from the uniformly doped layer to the low-concentration doped layer.
25. The semiconductor device of any one of claims 4 through 24 , characterized in that where Vg is a voltage applied to the gate electrode and Vt is the threshold voltage, if the absolute value of Vg−Vt is within a range of not less than 0 V and not more than 5 V, current flowing in a region of the channel layer which is located below the mid-position thereof is larger than current flowing in a region of the channel layer which is located above the mid-position.
26. The semiconductor device of any one of claims 1 through 25 , characterized by further comprising a drain layer formed by doping a lower portion of the semiconductor substrate with a high concentration of an impurity of the second conductivity type,
wherein the semiconductor device functions as a vertical MISFET.